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packm breaks with 1x1 micro-kernels #18

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fgvanzee opened this issue Jul 25, 2014 · 0 comments
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packm breaks with 1x1 micro-kernels #18

fgvanzee opened this issue Jul 25, 2014 · 0 comments

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@fgvanzee
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packm implicitly assumes that the register blocksizes are both non-unit. While this is not a bad assumption in practice, it would be nice to lift this constraint so that the right thing happens even if MR or NR (or both) happen to be 1. The problem boils down to the definition of the bli_is_row_stored_f() and bli_is_col_stored_f() macros, which only look at the row and column strides [of the packed micro-panel]. Naturally, if both are unit, then a "row-stored" mx1 micro-panel is indistinguishable from a "column-stored" 1xn micro-panel.
@heroxbd heroxbd mentioned this issue Feb 20, 2017
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niyas-sait pushed a commit to niyas-sait/blis that referenced this issue Feb 25, 2022
@ines @honnibal
Fix CI for Windows (flame#18)
02ac486 
* Update windows-x86_64.jsonl

* Update azure-pipelines.yml

* Delete .appveyor_generate_make.yml

* Update azure-pipelines.yml

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* Debug windows build

* Experiment

* Try adding conda-forge scripts

* Try using build from blis conda-forge

* Fix yaml

* Update azure-pipelines.yml

* Update azure-pipelines.yml

* Update azure-pipelines.yml

* Update build.sh

* Update build.sh

* Update azure-pipelines.yml

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* Update build.sh

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* Update build.sh

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* Update setup.py

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* Update setup.py

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* Update setup.py

* Update windows-x86_64.jsonl

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* Update setup.py

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* Reorganize old CI files

* Update azure-pipelines.yml

* Update setup.py

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* Update setup.py

* Update setup.py

* Update azure-pipelines.yml

* Update README.md [ci skip]

* Update azure-pipelines.yml


Co-authored-by: Matthew Honnibal <honnibal+gh@gmail.com>
Aaron-Hutchinson added a commit to sifive/sifive-blis that referenced this issue Apr 4, 2023
@Aaron-Hutchinson
Add scalv kernels (flame#18)
7082f6f
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