This repository contains common cells(Verilog) for use in projects.
Name | Description | Status |
---|---|---|
float_adder |
(32 bit) float point adder | finish |
float_mul |
(32 bit) float point multiplier | finish |
binary2bcd |
8-bit binary to bcd | finish |
gcd |
GCD of 2 integers | finish |
alu |
basic alu | todo |
cordic |
calculate arctan using cordic algorithm | todo |
fft |
fast fourier transform | todo |
Name | Description | Status |
---|---|---|
uart |
UART protocol(including sending and receiving module) | finish |
fifo_syn |
synchronous FIFO | todo |
fifo_asyn |
asynchronous FIFO | todo |
Name | Description | Status |
---|---|---|
ahb_lite |
simple implementation of AHB-Lite protocol | todo |
iicm |
iic master controller(using for controlling MP8864) | finish |
Name | Description | Status |
---|---|---|
keyboard |
scan keyboard | finish |
fsm |
Finite state machine generated by py | todo |
(2021.5.7)Add Makefile. Use vcs to simulate.