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rst_i should not be a required signal #1

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olofk opened this issue May 3, 2018 · 12 comments
Open

rst_i should not be a required signal #1

olofk opened this issue May 3, 2018 · 12 comments

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@olofk
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olofk commented May 3, 2018

3.4.0 lists rst_i as a required signal for masters and slaves. In practice, the rst_i signal should not always be needed. Even the example in A.7.2 does not include rst_i

(discovered by Alfred M. Szmidt)

@m-kru
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m-kru commented Sep 18, 2021

What page, which revision? I struggle to find it.

@ams
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ams commented Sep 18, 2021

It is rule 3.40, page 34-34 of B4. "As a minimum, ... MUST include the following signals: ... [RST_I], ...".

@m-kru
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m-kru commented Sep 18, 2021

Ok, I see. Doesn't it depend on the target FPGA/ASIC? With FPGA you do not need reset to bring the logic to the proper initial state. I am not sure how it is with ASIC nowadays, but more than 20 years ago I guess they needed reset to bring it to the known state after power up?

@rherveille
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rherveille commented Sep 18, 2021 via email

@ams
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ams commented Sep 18, 2021

Which is why it should be made optional, not a required signal. The example as such is even not compliant with the spec. The WB spec can't really make any guarantees that a core will work in ASIC.

@olofk
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olofk commented Sep 18, 2021

It's not just about FPGA/ASIC. It is fully possible to make some components with wishbone interfaces that are completely stateless (my wishbone multiplexer being such an example https://github.com/olofk/wb_intercon/blob/master/rtl/verilog/wb_mux.v).

Also, compare with e.g. AXI stream where only the tvalid signal is required IIRC. Even tdata and tready are optional because there exist perfectly valid use cases without them

@rherveille
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rherveille commented Sep 18, 2021 via email

@rherveille
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rherveille commented Sep 18, 2021 via email

@ams
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ams commented Sep 18, 2021

If a core doesn’t work in an ASIC it’s a bad core

Such comments are unhelpful and outright hostile to hobbyists that only have access to of the shelf FPGAs but can still write good cores without them working on an ASIC..

Not everyone has the means to try their cores on ASIC.

@m-kru
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m-kru commented Sep 19, 2021

@rherveille

It is bad practice to rely on FPGA configuration to set required signals to a known state.

If a core doesn’t work in an ASIC it’s a bad core

You state highly subjective theses without providing any arguments.

@rherveille
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rherveille commented Sep 19, 2021 via email

@ams
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ams commented Sep 19, 2021

Let's keep highly subjective and personal comments like this somewhere else.

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