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README.md

ethernet-fmc-axi-eth

Example design for the Quad Gigabit Ethernet FMC using 4 AXI Ethernet blocks.

Requirements

This project is designed for version 2019.2 of the Xilinx tools (Vivado/Vitis/PetaLinux). If you are using an older version of the Xilinx tools, then refer to the release tags to find the version of this repository that matches your version of the tools.

In order to test this design on hardware, you will need the following:

Supported carrier boards

8-port Support (2 x Ethernet FMCs)

The only Evaluation boards that can support two Ethernet FMCs simultaneously are the KC705, KCU105, ZC702 and VC707.

This repository contains example designs for using 2 x Ethernet FMCs on the same carrier. They all use 8 Xilinx AXI Ethernet Subsystem IPs that are configured with DMAs, except for the ZC702 design, which is configured with FIFOs. The reason for this is a lack of FPGA resources as using 8 MACs configured with DMAs requires more resources than is contained in the Zynq device of that board.

These notes provide more details on 8-port support:

  • The KC705 and VC707 each have two FMC connectors that support the Ethernet FMC (use kc705-lpc-hpc.xdc and vc707-hpc2-hpc1.xdc respectively).
  • The KCU105 can support two Ethernet FMCs however the LPC only supports 3 ports so the dual design contains only 7 ports total. The critical block which does not pass timing requirements is the axi_mem_intercon.
  • The ZC702 has two FMC connectors that can support the Ethernet FMC, however note that the Zynq device on this board has limited FPGA resources for supporting 8 x Xilinx AXI Ethernet IPs (ie. the MACs). The device has enough resources when the 8 MACs are configured with FIFOs, however there are insufficient resources to configure them with DMAs. Alternatively, you could use a MAC that requires less resources. (use zc702-lpc2-lpc1.xdc)
  • The ZC706 has two FMC connectors, but only one (the LPC) can support the Ethernet FMC (see detail in board specific notes below).

Description

This project demonstrates the use of the Opsero Quad Gigabit Ethernet FMC. The design contains 4 AXI Ethernet blocks configured with DMAs.

Block diagram

Note: Zynq PS block is replaced by MicroBlaze processor for the Artix, Kintex and Virtex boards.

Build instructions

To use the sources in this repository, please follow these steps:

Windows users

  1. Download the repo as a zip file and extract the files to a directory on your hard drive --OR-- Git users: clone the repo to your hard drive
  2. Open Windows Explorer, browse to the repo files on your hard drive.
  3. In the Vivado directory, you will find multiple batch files (*.bat). Double click on the batch file that is appropriate to your hardware, for example, double-click build-zedboard.bat if you are using the ZedBoard. This will generate a Vivado project for your hardware platform.
  4. Run Vivado and open the project that was just created.
  5. Click Generate bitstream.
  6. When the bitstream is successfully generated, select File->Export->Export Hardware. In the window that opens, tick "Include bitstream" and "Local to project".
  7. Return to Windows Explorer and browse to the Vitis directory in the repo.
  8. Double click the build-vitis.bat batch file. The batch file will run the build-vitis.tcl script and build the Vitis workspace containing the hardware design and the software application.
  9. Run Xilinx Vitis and select the workspace to be the Vitis directory of the repo.
  10. Connect and power up the hardware.
  11. Open a Putty terminal to view the UART output.
  12. In Vitis, select Xilinx Tools->Program FPGA.
  13. Right-click on the application and select Run As->Launch on Hardware (Single Application Debug)

Linux users

  1. Download the repo as a zip file and extract the files to a directory on your hard drive --OR-- Git users: clone the repo to your hard drive
  2. Launch the Vivado GUI.
  3. Open the Tcl console from the Vivado welcome page. In the console, cd to the repo files on your hard drive and into the Vivado subdirectory. For example: cd /media/projects/ethernet-fmc-axi-eth/Vivado.
  4. In the Vivado subdirectory, you will find multiple Tcl files. To list them, type exec ls {*}[glob *.tcl]. Determine the Tcl script for the example project that you would like to generate (for example: build-zedboard.tcl), then source the script in the Tcl console: For example: source build-zedboard.tcl
  5. Vivado will run the script and generate the project. When it's finished, click Generate bitstream.
  6. When the bitstream is successfully generated, select File->Export->Export Hardware. In the window that opens, tick "Include bitstream" and "Local to project".
  7. To build the Vitis workspace, open a Linux command terminal and cd to the Vitis directory in the repo.
  8. The Vitis directory contains the build-vitis.tcl script that will build the Vitis workspace containing the hardware design and the software application. Run the build script by typing the following command: <path-of-xilinx-vitis>/bin/xsct build-vitis.tcl. Note that you must replace <path-of-xilinx-vitis> with the actual path to your Xilinx Vitis installation.
  9. Run Xilinx Vitis and select the workspace to be the Vitis subdirectory of the repo.
  10. Connect and power up the hardware.
  11. Open a Putty terminal to view the UART output.
  12. In Vitis, select Xilinx Tools->Program FPGA.
  13. Right-click on the application and select Run As->Launch on Hardware (Single Application Debug)

Stand-alone software application

The software application used to test these projects is the lwIP Echo Server example that is built into Xilinx Vitis. The application relies on the lwIP library (also built into Xilinx Vitis) but with a few modifications. The modified version of the lwIP library is contained in the EmbeddedSw directory, which is added as a local software repository to the Vitis workspace. See the "README.md" file in the Vitis directory for more information.

Single port limit for lwIP echo server

The echo server example design currently can only target one Ethernet port at a time. Selection of the Ethernet port can be changed by modifying the defines contained in the platform_config.h file in the application sources. Set PLATFORM_EMAC_BASEADDR to one of the following values depending on the port you want to target:

  • Ethernet FMC Port 0: XPAR_AXIETHERNET_0_BASEADDR
  • Ethernet FMC Port 1: XPAR_AXIETHERNET_1_BASEADDR
  • Ethernet FMC Port 2: XPAR_AXIETHERNET_2_BASEADDR
  • Ethernet FMC Port 3: XPAR_AXIETHERNET_3_BASEADDR

PetaLinux

This repo contains a script and configuration files for a PetaLinux project for each one of the hardware platforms. To build the PetaLinux project, please refer to the "README.md" file in the PetaLinux subdirectory of this repo.

Board specific notes

AC701

  • The AC701's on-board Ethernet port is not connected in this design.
  • This design includes a reset GPIO so that the MicroBlaze can reset itself from PetaLinux.

KC705

  • The KC705's on-board Ethernet port is connected to AXI EthernetLite IP in these designs.
  • This design includes a reset GPIO so that the MicroBlaze can reset itself from PetaLinux.

VC707 & VC709

  • These boards can only support the 1.8V version Ethernet FMC. The device on these boards have only HP (high-performance) I/Os which do not support 2.5V levels.

ZC706

  • Zynq-7000 ZC706 Evaluation board (HPC)
    • HPC connector: Pins LA18_CC and LA17_CC of the HPC connector are routed to non-clock-capable pins so they cannot properly receive the RGMII receive clocks for ports 2 and 3 of the Ethernet FMC. The constraints file zc706-hpc.xdc is provided for reference, however it will not pass compilation with the Xilinx tools due to this problem.

KCU105

  • This board can only support the 1.8V version Ethernet FMC. The device on this board has only HP (high-performance) I/Os which do not support 2.5V levels.
  • KCU105 board design for the LPC connector is configured for only 3 ports as there is a strange placement error which occurs when trying to build a design with 4 ports. The placement error has to do with IDELAYs and I have not reached a solution for this yet. There is no such problem with the HPC for this board.

ZCU102

  • These designs support the ZCU102 Rev 1.0 and newer boards. Use a commit before 2016-02-13 for the older Rev-D board design. Note that the FMC pinouts differ between Rev 1.0 and Rev D: https://www.xilinx.com/support/answers/68050.html
  • This board can only support the 1.8V version Ethernet FMC. The device on this board has only HP (high-performance) I/Os which do not support 2.5V levels.
  • The HPC1 design only supports 2 ports due to the HPC1 pin assignment to the Zynq US+ (see constraints file for more details).

PicoZed

Differences between designs

This repository contains a Vivado design for these PicoZed versions: 7Z020, 7Z015 and 7Z030. The main differences between the designs are described below:

  • 7Z020: We use 4x AXI Ethernet IPs. The constraints file uses the 2.5V IO standards.
  • 7Z015: We use 4x AXI Ethernet IPs. The constraints file uses the 2.5V IO standards.
  • 7Z030: We use 4x AXI Ethernet IPs. The constraints file uses the 1.8V IO standards because this device has HP I/Os.

Installation of MicroZed, PicoZed and UltraZed board definition files

To use the projects for the MicroZed, PicoZed and UltraZed, you must first install the board definition files for those boards into your Vivado and Vitis installation.

The following folders contain the board definition files and can be found in this project repository at this location:

https://github.com/Avnet/bdf

  • microzed_7010
  • microzed_7020
  • picozed_7010_fmc2
  • picozed_7015_fmc2
  • picozed_7020_fmc2
  • picozed_7030_fmc2
  • ultrazed_7ev_cc

Copy those folders and their contents into the C:\Xilinx\Vivado\2019.2\data\boards\board_files folder (this may be different on your machine, depending on your Vivado installation directory). You also need to make a copy into the Vitis installation at this location: C:\Xilinx\Vitis\2019.2\data\boards\board_files.

Microblaze design differences

The designs for AC701, KC705, VC707, VC709 & KCU105 all use the Microblaze soft processor. These designs have some specific differences when compared to the Zynq based designs:

  • MIG - the MIG is required to exploit the DDR3/4 memory of the eval boards.
  • AXI Timer - the lwIP echo server application requires a timer (Microblaze does not have one inherently).
  • AXI UART16550 - the lwIP echo server application requires a UART for console output.

Troubleshooting

Check the following if the project fails to build or generate a bitstream:

1. Are you using the correct version of Vivado for this version of the repository?

Check the version specified in the Requirements section of this readme file. Note that this project is regularly maintained to the latest version of Vivado and you may have to refer to an earlier commit of this repo if you are using an older version of Vivado.

2. Did you correctly follow the Build instructions in this readme file?

All the projects in the repo are built, synthesised and implemented to a bitstream before being committed, so if you follow the instructions, there should not be any build issues.

3. Did you copy/clone the repo into a short directory structure?

Vivado doesn't cope well with long directory structures, so copy/clone the repo into a short directory structure such as C:\projects\. When working in long directory structures, you can get errors relating to missing files, particularly files that are normally generated by Vivado (FIFOs, etc).

For more information

If you need more information on whether the Ethernet FMC is compatible with your carrier, please contact me here. Just provide me with the pinout of your carrier and I'll be happy to check compatibility and generate a Vivado constraints file for you.

Contribute

We encourage contribution to these projects. If you spot issues or you want to add designs for other platforms, please make a pull request.

About us

This project was developed by Opsero Inc., a tight-knit team of FPGA experts delivering FPGA products and design services to start-ups and tech companies. Follow our blog, FPGA Developer, for news, tutorials and updates on the awesome projects we work on.

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Example design for the Ethernet FMC using 4 AXI Ethernet Subsystem IP blocks

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