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Zynq GEM Reference Designs for Ethernet FMC

Description

This project demonstrates the use of the Opsero Quad Gigabit Ethernet FMC. The design uses the GMII-to-RGMII IP core to connect the hard GEMs of the Zynq PS to the Ethernet FMC PHYs. The designs target both the Zynq and ZynqMP devices and are illustrated by the block diagrams below.

Zynq Design

Zynq GEM design block diagram

ZynqMP Design

ZynqMP GEM design block diagram

Important links:

Requirements

This project is designed for version 2020.2 of the Xilinx tools (Vivado/Vitis/PetaLinux). If you are using an older version of the Xilinx tools, then refer to the release tags to find the version of this repository that matches your version of the tools.

In order to test this design on hardware, you will need the following:

Contribute

We encourage contribution to these projects. If you spot issues or you want to add designs for other platforms, please make a pull request.

About us

This project was developed by Opsero Inc., a tight-knit team of FPGA experts delivering FPGA products and design services to start-ups and tech companies. Follow our blog, FPGA Developer, for news, tutorials and updates on the awesome projects we work on.

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Example design for the Ethernet FMC using the hard GEMs of the Zynq

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