Example design for the Ethernet FMC using the hard GEMs of the Zynq
C Tcl Batchfile



Example design for using the Quad Gigabit Ethernet FMC with the Zynq PS hard Gigabit Ethernet MACs (GEM) and the GMII-to-RGMII IP.

Supported boards


This project demonstrates the use of the Opsero Quad Gigabit Ethernet FMC. The design demonstrates use of the GMII-to-RGMII IP core to connect the hard GEMs of the Zynq PS to the Ethernet FMC PHYs. All designs use the hard GEMs but some also use AXI Ethernet Subsystem IP.

Ethernet FMC Quad Gig AXI Ethernet


Board specific notes


  • The ZCU102 board does not route LA01_CC and LA18_CC signals of the HPC0 and HPC1 connectors to clock capable pins, so the designs for the ZCU102 board use only 2 ports: Port 0 and 2.

ZedBoard and MicroZed

When changing ETH_FMC_PORT from 0-2 to 3 (ie. when switching to GEM1), it has been noticed that you have to power cycle the board. When the SDK project is configured for AXI Ethernet, it must make some Zynq configurations that are not compatible with the GEM1 configuration.


Uses Zynq Fabric clocks

To generate the 125MHz and 200MHz clocks required by the AXI Ethernet IPs, this design uses two Zynq fabric clocks rather than using the Ethernet FMC's on-board 125MHz clock. Generally this is due to resource limitations of the MicroZed 7Z010, but to be more specific:

  • Using the on-board 125MHz clock + Zynq fabric 200MHz clock leads to a timing closure problem that I have not yet been able to get around.
  • Using the on-board 125MHz clock into a clock wizard to generate the 200MHz clock is not possible due to the Zynq 7Z010 only containing two MMCMs.
Installation of MicroZed board definition files

To use this project, you must first install the board definition files for the MicroZed into your Vivado installation.

The following folders contain the board definition files and can be found in this project repository at this location:


  • microzed_7010
  • microzed_7020

Copy those folders and their contents into the C:\Xilinx\Vivado\2016.4\data\boards\board_files folder (this may be different on your machine, depending on your Vivado installation directory).

Building the SDK workspace

The software application used to test these projects is the lwIP Echo Server example that is built into Xilinx SDK. The application relies on the lwIP library (also built into Xilinx SDK) but with a few modifications. The modified version of the lwIP library is contained in the EmbeddedSw directory, which is added as a local SDK repository to the SDK workspace.

Instructions for building the SDK workspace can be found in the SDK directory of this repo.

Single port limit

The echo server example design currently can only target one Ethernet port at a time. Selection of the Ethernet port can be changed by modifying the defines contained in the platform_config.h file in the application sources. Set PLATFORM_EMAC_BASEADDR to one of the following values depending on the port you want to target, and the hardware platform:

ZedBoard and MicroZed designs
  • Ethernet FMC Port 3: XPAR_XEMACPS_1_BASEADDR
ZCU102 designs (HPC0 and HPC1)
  • Ethernet FMC Port 0: XPAR_XEMACPS_0_BASEADDR
  • Ethernet FMC Port 2: XPAR_XEMACPS_1_BASEADDR
BSP Setting
  • When using ports that use AXI Ethernet IP, the BSP setting "use_axieth_on_zynq" must be set to 1.
  • When using ports that use Zynq GEM, the BSP setting "use_axieth_on_zynq" must be set to 0.

To change BSP settings: right click on the BSP and click Board Support Package Settings from the context menu.


Feel free to modify the code for your specific application.

About us

This project was developed by Opsero Inc., a tight-knit team of FPGA experts delivering FPGA products and design services to start-ups and tech companies. Follow our blog, FPGA Developer, for news, tutorials and updates on the awesome projects we work on.