fix(cygnet): typo

regenerate cmake files. Signed-off-by: Frederic Pillon <frederic.pillon@st.com>
fpistm · Jun 18, 2024 · 6c0c006 · 6c0c006
1 parent ced1323
commit 6c0c006
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Showing 3 changed files with 88 additions and 88 deletions.
diff --git a/boards.txt b/boards.txt
@@ -10818,8 +10818,8 @@ Blues.menu.pnum.CYGNET.build.series=STM32L4xx
 Blues.menu.pnum.CYGNET.build.product_line=STM32L433xx
 Blues.menu.pnum.CYGNET.build.variant=STM32L4xx/L433C(B-C)(T-U)_L443CC(T-U)
 Blues.menu.pnum.CYGNET.build.peripheral_pins=-DCUSTOM_PERIPHERAL_PINS
-Blues.menu.pnum.CYGNET_L4.build.vid=0x30A4
-Blues.menu.pnum.CYGNET_L4.build.pid=0x0003
+Blues.menu.pnum.CYGNET.build.vid=0x30A4
+Blues.menu.pnum.CYGNET.build.pid=0x0003
 
 # Upload menu
 Blues.menu.upload_method.swdMethod=STM32CubeProgrammer (SWD)

diff --git a/cmake/boards_db.cmake b/cmake/boards_db.cmake
@@ -4166,6 +4166,88 @@ target_link_options(CoreBoard_F401RC_hid INTERFACE
 )
 
 
+# CYGNET
+# -----------------------------------------------------------------------------
+
+set(CYGNET_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32L4xx/L433C(B-C)(T-U)_L443CC(T-U)")
+set(CYGNET_MAXSIZE 262144)
+set(CYGNET_MAXDATASIZE 65536)
+set(CYGNET_MCU cortex-m4)
+set(CYGNET_FPCONF "fpv4-sp-d16-hard")
+add_library(CYGNET INTERFACE)
+target_compile_options(CYGNET INTERFACE
+  "SHELL:-DSTM32L433xx  "
+  "SHELL:-DCUSTOM_PERIPHERAL_PINS"
+  "SHELL:"
+  "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard"
+  -mcpu=${CYGNET_MCU}
+)
+target_compile_definitions(CYGNET INTERFACE
+  "STM32L4xx"
+	"ARDUINO_CYGNET"
+	"BOARD_NAME=\"CYGNET\""
+	"BOARD_ID=CYGNET"
+	"VARIANT_H=\"variant_CYGNET.h\""
+)
+target_include_directories(CYGNET INTERFACE
+  ${CMAKE_CURRENT_LIST_DIR}/../system/STM32L4xx
+  ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Inc
+  ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Src
+  ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/
+  ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/Templates/gcc/
+  ${CYGNET_VARIANT_PATH}
+)
+
+target_link_options(CYGNET INTERFACE
+  "LINKER:--default-script=${CYGNET_VARIANT_PATH}/ldscript.ld"
+  "LINKER:--defsym=LD_FLASH_OFFSET=0x0"
+	"LINKER:--defsym=LD_MAX_SIZE=262144"
+	"LINKER:--defsym=LD_MAX_DATA_SIZE=65536"
+  "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard"
+  -mcpu=${CYGNET_MCU}
+)
+
+add_library(CYGNET_serial_disabled INTERFACE)
+target_compile_options(CYGNET_serial_disabled INTERFACE
+  "SHELL:"
+)
+add_library(CYGNET_serial_generic INTERFACE)
+target_compile_options(CYGNET_serial_generic INTERFACE
+  "SHELL:-DHAL_UART_MODULE_ENABLED"
+)
+add_library(CYGNET_serial_none INTERFACE)
+target_compile_options(CYGNET_serial_none INTERFACE
+  "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE"
+)
+add_library(CYGNET_usb_CDC INTERFACE)
+target_compile_options(CYGNET_usb_CDC INTERFACE
+  "SHELL:-DUSBCON  -DUSBD_VID=0x30A4 -DUSBD_PID=0x0003 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB"
+)
+add_library(CYGNET_usb_CDCgen INTERFACE)
+target_compile_options(CYGNET_usb_CDCgen INTERFACE
+  "SHELL:-DUSBCON  -DUSBD_VID=0x30A4 -DUSBD_PID=0x0003 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC"
+)
+add_library(CYGNET_usb_HID INTERFACE)
+target_compile_options(CYGNET_usb_HID INTERFACE
+  "SHELL:-DUSBCON  -DUSBD_VID=0x30A4 -DUSBD_PID=0x0003 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE"
+)
+add_library(CYGNET_usb_none INTERFACE)
+target_compile_options(CYGNET_usb_none INTERFACE
+  "SHELL:"
+)
+add_library(CYGNET_xusb_FS INTERFACE)
+target_compile_options(CYGNET_xusb_FS INTERFACE
+  "SHELL:"
+)
+add_library(CYGNET_xusb_HS INTERFACE)
+target_compile_options(CYGNET_xusb_HS INTERFACE
+  "SHELL:-DUSE_USB_HS"
+)
+add_library(CYGNET_xusb_HSFS INTERFACE)
+target_compile_options(CYGNET_xusb_HSFS INTERFACE
+  "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS"
+)
+
 # DAISY_PATCH_SM
 # -----------------------------------------------------------------------------
 
@@ -106755,15 +106837,15 @@ target_compile_options(SWAN_R5_serial_none INTERFACE
 )
 add_library(SWAN_R5_usb_CDC INTERFACE)
 target_compile_options(SWAN_R5_usb_CDC INTERFACE
-  "SHELL:-DUSBCON  -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB"
+  "SHELL:-DUSBCON  -DUSBD_VID=0x30A4 -DUSBD_PID=0x0002 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB"
 )
 add_library(SWAN_R5_usb_CDCgen INTERFACE)
 target_compile_options(SWAN_R5_usb_CDCgen INTERFACE
-  "SHELL:-DUSBCON  -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC"
+  "SHELL:-DUSBCON  -DUSBD_VID=0x30A4 -DUSBD_PID=0x0002 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC"
 )
 add_library(SWAN_R5_usb_HID INTERFACE)
 target_compile_options(SWAN_R5_usb_HID INTERFACE
-  "SHELL:-DUSBCON  -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE"
+  "SHELL:-DUSBCON  -DUSBD_VID=0x30A4 -DUSBD_PID=0x0002 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE"
 )
 add_library(SWAN_R5_usb_none INTERFACE)
 target_compile_options(SWAN_R5_usb_none INTERFACE
@@ -106782,88 +106864,6 @@ target_compile_options(SWAN_R5_xusb_HSFS INTERFACE
   "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS"
 )
 
-# CYGNET
-# -----------------------------------------------------------------------------
-
-set(CYGNET_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32L4xx/L433C(B-C)(T-U)_L443CC(T-U)")
-set(CYGNET_MAXSIZE 262144)
-set(CYGNET_MAXDATASIZE 65536)
-set(CYGNET_MCU cortex-m4)
-set(CYGNET_FPCONF "fpv4-sp-d16-hard")
-add_library(CYGNET INTERFACE)
-target_compile_options(CYGNET INTERFACE
-  "SHELL:-DSTM32L4xx  "
-  "SHELL:-DCUSTOM_PERIPHERAL_PINS"
-  "SHELL:"
-  "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard"
-  -mcpu=${CYGNET_MCU}
-)
-target_compile_definitions(CYGNET INTERFACE
-  "STM32L4xx"
-	"ARDUINO_CYGNET"
-	"BOARD_NAME=\"CYGNET\""
-	"BOARD_ID=CYGNET"
-	"VARIANT_H=\"variant_CYGNET.h\""
-)
-target_include_directories(CYGNET INTERFACE
-  ${CMAKE_CURRENT_LIST_DIR}/../system/STM32L4xx
-  ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Inc
-  ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Src
-  ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/
-  ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/Templates/gcc/
-  ${CYGNET_VARIANT_PATH}
-)
-
-target_link_options(CYGNET INTERFACE
-  "LINKER:--default-script=${CYGNET_VARIANT_PATH}/ldscript.ld"
-  "LINKER:--defsym=LD_FLASH_OFFSET=0x0"
-	"LINKER:--defsym=LD_MAX_SIZE=262144"
-	"LINKER:--defsym=LD_MAX_DATA_SIZE=65536"
-  "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard"
-  -mcpu=${CYGNET_MCU}
-)
-
-add_library(CYGNET_serial_disabled INTERFACE)
-target_compile_options(CYGNET_serial_disabled INTERFACE
-  "SHELL:"
-)
-add_library(CYGNET_serial_generic INTERFACE)
-target_compile_options(CYGNET_serial_generic INTERFACE
-  "SHELL:-DHAL_UART_MODULE_ENABLED"
-)
-add_library(CYGNET_serial_none INTERFACE)
-target_compile_options(CYGNET_serial_none INTERFACE
-  "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE"
-)
-add_library(CYGNET_usb_CDC INTERFACE)
-target_compile_options(CYGNET_usb_CDC INTERFACE
-  "SHELL:-DUSBCON  -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB"
-)
-add_library(CYGNET_usb_CDCgen INTERFACE)
-target_compile_options(CYGNET_usb_CDCgen INTERFACE
-  "SHELL:-DUSBCON  -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC"
-)
-add_library(CYGNET_usb_HID INTERFACE)
-target_compile_options(CYGNET_usb_HID INTERFACE
-  "SHELL:-DUSBCON  -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE"
-)
-add_library(CYGNET_usb_none INTERFACE)
-target_compile_options(CYGNET_usb_none INTERFACE
-  "SHELL:"
-)
-add_library(CYGNET_xusb_FS INTERFACE)
-target_compile_options(CYGNET_xusb_FS INTERFACE
-  "SHELL:"
-)
-add_library(CYGNET_xusb_HS INTERFACE)
-target_compile_options(CYGNET_xusb_HS INTERFACE
-  "SHELL:-DUSE_USB_HS"
-)
-add_library(CYGNET_xusb_HSFS INTERFACE)
-target_compile_options(CYGNET_xusb_HSFS INTERFACE
-  "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS"
-)
-
 # THUNDERPACK_F411
 # -----------------------------------------------------------------------------
 

diff --git a/variants/STM32L4xx/L433C(B-C)(T-U)_L443CC(T-U)/CMakeLists.txt b/variants/STM32L4xx/L433C(B-C)(T-U)_L443CC(T-U)/CMakeLists.txt
@@ -22,8 +22,8 @@ add_library(variant_bin STATIC EXCLUDE_FROM_ALL
   generic_clock.c
   PeripheralPins.c
   PeripheralPins_CYGNET.c
-  variant_generic.cpp
   variant_CYGNET.cpp
+  variant_generic.cpp
 )
 target_link_libraries(variant_bin PUBLIC variant_usage)