I'm an ASIC/FPGA digital designer engineer. I like verilog and VHDL. I really help sw guys because I'm close to their world.
-
Istituto Italiano di Tecnologia
- https://www.linkedin.com/in/francesco-diotalevi-3023b2164/
Block or Report
Block or report francescodiotalevi
Report abuse
Contact GitHub support about this user’s behavior. Learn more about reporting abuse.
Report abusePopular repositories Loading
-
-
-
linux-zynq-stable
linux-zynq-stable PublicForked from andreamerello/linux-zynq-stable
Fork of linux-stable.git with my patches for zynq-based boards (Zed, MYIR..)
C
-
u-boot-xlnx
u-boot-xlnx PublicForked from Xilinx/u-boot-xlnx
The official Xilinx u-boot repository
C
-
Something went wrong, please refresh the page to try again.
If the problem persists, check the GitHub status page or contact support.
If the problem persists, check the GitHub status page or contact support.