LDV - a better way to deal with 16-bit immediate value

[hlide]

Since you word is 16-bit wide, you may split it into 2×8-bit, and keep two bits of immediate (SS bits) to select a special operation.

In MIPS, you have LUI instruction which sets a register with imm16 left shifted by 16 bits. Then you can use ADDIU or ORI to add/or-ize the register with a signed 16-bit immediate value, allowing in two instructions to set a 32-bit immediate value to a register. ARM Cortex architecture also have a similar way.

So in your case, it could be:

• OO:00 – MVI Dr, imm8 –> Dr = unsigned(imm8)
• OO:01 – ADI Dr, imm8 –> Dr = Dr + signed(imm8)
• OO:10 – MUI Dr, imm8 –> Dr = unsigned(imm8) shl 8
• OO:11 – AUI Dr, imm8 –> Dr = Dr + signed(imm8) shl 8

And

|LDV| D, V | VVVVVVVVVVDD0001 | Load a value into destination register.

becomes

|LDV| D, V, O | VVVVVVVVOODD0001 | Load a value into destination register.

with pseudos

|MVI| D, V | VVVVVVVV00DD0001 | Set a zero-extended lower byte to destination register.
|ADI| D, V | VVVVVVVV01DD0001 | Set a zero-extended lower byte to destination register.
|MUI| D, V | VVVVVVVV10DD0001 | Set a byte left shifted by 8 bits to destination register.
|AUI| D, V | VVVVVVVV11DD0001 | Add a byte left shifted by 8 bits to destination register.

Mnemonics stand for:

• MVI: MoVe Immediate,
• ADI: ADd Immediate,
• MUI: Move Upper Immediate,
• AUI: Add Upper Immediate.

The rationale is:
– the 8-bit immediate is zero/signed-extended respectively when bit 0 of SS is 0/1.
– the effective immediate value is set with the extended 8-bit immediate left shifted by 0/8 bits respectively when bit 1 of SS is 0/1,
– the effective immediate value is set/added respectively to the destination register when bit 0 of SS is 0/1.

As a result,

• you can ditch INC/DEC Dr because you can use ADI Dr,+1/-1,
• you can use a loop step different to -1/+1 with only one instruction,
• you can use that pair: MVI Dr, 0xLL; AUI Dr, 0xHH <=> Dr = 0x00LL + 0xHH00 <=> Dr = 0xHHLL and define a pseudo MVA Dr, 0xHHLL,
• you can add/substract a big constant amount: AUI Dr, 0xHH;ADI Dr,0xLL <=> Dr = Dr + 0xHH00 + 0x00LL <=> Dr = Dr + 0xHHLL if 0xLL is inferior or equals to 0x7f,
• you can add/substract a big constant amount: AUI Dr, 0xHH+1; ADI Dr, 0xLL <=> Dr = Dr + (0xHH00+0x0100) + (0xffLL) <=> Dr = Dr + 0xHHLL if 0xLL is greater than 0x7f.
• you can define a pseudo ADA Dr, 0xHHLL for the previous two points and which issues the right pair according to the sign bit of 0xLL.

[francisrstokes]

Hey thanks for the feedback! The encoding strategy you've proposed is really nice compared with my brute force LDV16 pseudo approach 😄. The only problem I could possibly see is that all numbers are unsigned, so it wouldn't be possible to use ADI d, -1.

That said, a lot of what you've said could definitely improve the language. Would you be interested in opening a pull request with you're proposed changes?

[hlide]

What do you mean by "all numbers are unsigned"? for a 16-bit addition, the result with signed or unsigned addends is the same. For instance, 0xFFFE + 0xFFFF = 0xFFFD. 0xFFFD can be seen as 65533 or -3, it's just a subjective viewpoint. When using ADD mode through bit 0 in OO, you just need to sign-extend the immediate value before adding it to register.

[hlide]

"opening a pull request with you're proposed changes": do you suggest for me to clone your project, do the changes and then open pull request here?

[francisrstokes]

for a 16-bit addition, the result with signed or unsigned addends is the same. For instance, 0xFFFE + 0xFFFF = 0xFFFD. 0xFFFD can be seen as 65533 or -3, it's just a subjective viewpoint

Ah good point. As for pull request, yes that's normally the easiest way.

[hlide]

hum, there are that assembler and that bf compiler... if I don't want to touch that bf compiler, I'd better to keep LDV16 but as a pseudo using the new instruction and define LDV as a pseudo as well. I could also keep INC and DEC the same way. But I would need to rename the real instruction LDV with another name - unless there is a way to have an optional third argument, that is LDV D, imm <=> LDV D, imm, 0. Is that possible?

[francisrstokes]

3rd argument can definitely work. While I agree the names are not the best, I'd rather take the path of least resistance when it comes to changes.

[francisrstokes]

Merged proposal to master