Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Jump to bottom

Fix trailing spaces #2

Merged
merged 1 commit into from
Jul 19, 2023
Merged

Fix trailing spaces #2

Changes from all commits
Commits
Show all changes
1 commit
Select commit
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
38 changes: 19 additions & 19 deletions README.md
View file
Open in desktop
Original file line number Diff line number Diff line change
@@ -1,35 +1,35 @@
# riscv_em
This is a risc-v emulator written in plain C.
It started as a fun project a while ago and is now capable of doing a few things (but still just a hobby, won't be big and professional like qemu ;)
This is a risc-v emulator written in plain C.
It started as a fun project a while ago and is now capable of doing a few things (but still just a hobby, won't be big and professional like qemu ;)

### Ever wanted to know what the absolute minimum requirements are to run linux?
riscv_em is the answer. Yes, the emulator is capable of running Linux.

One goal of this project is to be easily able to understand its source code and thus also the risc-v isa. You can also see this project as an attempt to directly translate the RISC-V ISA specs (Currently Unprivileged Spec v.20191213 and Privileged Spec v.20190608) into plain C.
Implementation focus is simplicity NOT efficiency! Altough I always try to improve it's performance whenever possible, as long as the code does not suffer losses in readability!
One goal of this project is to be easily able to understand its source code and thus also the risc-v isa. You can also see this project as an attempt to directly translate the RISC-V ISA specs (Currently Unprivileged Spec v.20191213 and Privileged Spec v.20190608) into plain C.
Implementation focus is simplicity NOT efficiency! Altough I always try to improve it's performance whenever possible, as long as the code does not suffer losses in readability!

Currently the emulator supports RV32IMA and RV64IMA instructions.
Furthermore it implements a CLINT (Core-Local Interrupt Controller) and also a PLIC (Platform Level Interrupt Controller), as well as a simple UART.
Currently the emulator supports RV32IMA and RV64IMA instructions.
Furthermore it implements a CLINT (Core-Local Interrupt Controller) and also a PLIC (Platform Level Interrupt Controller), as well as a simple UART.

## UPDATE 2021: Now the emulator also fully implements PMP and MMU.
Please see https://github.com/franzflasch/linux_for_riscv_em for a how-to-build appropriate linux images.

* MMU support is currently only available for RV32 (Sv32). Support for RV64 MMU (Sv39, Sv48) will follow.
* NOMMU is currently only supported for RV64 due to the kernel at the time of this writing only supports this for RV64.

### How-To build RV64-nommu:
```console
mkdir build && cd build
cmake -DRV_ARCH=64 ..
make
```
### How-To build RV64-nommu:
```console
mkdir build && cd build
cmake -DRV_ARCH=64 ..
make
```

### How-To build RV32-mmu:
```console
mkdir build && cd build
cmake -DRV_ARCH=32 ..
make
```
### How-To build RV32-mmu:
```console
mkdir build && cd build
cmake -DRV_ARCH=32 ..
make
```

### Build the device tree binaries for RV64-nommu and RV32-mmu (device-tree-compiler needed):
```sh
Expand All @@ -38,7 +38,7 @@ cd dts
```

### Build a linux image for this emulator:
Please see https://github.com/franzflasch/linux_for_riscv_em
Please see https://github.com/franzflasch/linux_for_riscv_em

### Start the emulator and load (uc)linux (RV64-nommu):
```sh
Expand Down
Loading