* Added HasCoreMonitor trait to HasTiles trait (#1797)

* Moved CoreMonitorBundle class to util package

src/main/scala/rocket/RocketCore.scala

@@ -802,24 +802,10 @@ class Rocket(tile: RocketTile)(implicit p: Parameters) extends CoreModule()(p)
   val icache_blocked = !(io.imem.resp.valid || RegNext(io.imem.resp.valid))
   csr.io.counters foreach { c => c.inc := RegNext(perfEvents.evaluate(c.eventSel)) }
 
-  class CoreMonitorBundle extends Bundle {
-    val hartid = UInt(width = hartIdLen)
-    val time = UInt(width = 32)
-    val valid = Bool()
-    val pc = UInt(width = vaddrBitsExtended)
-    val wrdst = UInt(width = 5)
-    val wrdata = UInt(width = xLen)
-    val wren = Bool()
-    val rd0src = UInt(width = 5)
-    val rd0val = UInt(width = xLen)
-    val rd1src = UInt(width = 5)
-    val rd1val = UInt(width = xLen)
-    val inst = UInt(width = 32)
-  }
-  val coreMonitorBundle = Wire(new CoreMonitorBundle)
+  val coreMonitorBundle = Wire(new CoreMonitorBundle(xLen))
 
   coreMonitorBundle.hartid := io.hartid
-  coreMonitorBundle.time := csr.io.time(31,0)
+  coreMonitorBundle.timer := csr.io.time(31,0)
   coreMonitorBundle.valid := csr.io.trace(0).valid && !csr.io.trace(0).exception
   coreMonitorBundle.pc := csr.io.trace(0).iaddr(vaddrBitsExtended-1, 0)
   coreMonitorBundle.wrdst := Mux(rf_wen && !(wb_set_sboard && wb_wen), rf_waddr, UInt(0))
@@ -831,8 +817,6 @@ class Rocket(tile: RocketTile)(implicit p: Parameters) extends CoreModule()(p)
   coreMonitorBundle.rd1val := Reg(next=Reg(next=ex_rs(1)))
   coreMonitorBundle.inst := csr.io.trace(0).insn
 
-  p(BundleMonitorKey).foreach { _ ("rocket_core_monitor", coreMonitorBundle) }
-
   if (enableCommitLog) {
     val t = csr.io.trace(0)
     val rd = wb_waddr
@@ -861,7 +845,7 @@ class Rocket(tile: RocketTile)(implicit p: Parameters) extends CoreModule()(p)
   }
   else {
     printf("C%d: %d [%d] pc=[%x] W[r%d=%x][%d] R[r%d=%x] R[r%d=%x] inst=[%x] DASM(%x)\n",
-         coreMonitorBundle.hartid, coreMonitorBundle.time, coreMonitorBundle.valid,
+         coreMonitorBundle.hartid, coreMonitorBundle.timer, coreMonitorBundle.valid,
          coreMonitorBundle.pc,
          coreMonitorBundle.wrdst, coreMonitorBundle.wrdata, coreMonitorBundle.wren,
          coreMonitorBundle.rd0src, coreMonitorBundle.rd0val,

src/main/scala/subsystem/HasTiles.scala

@@ -17,7 +17,7 @@ class ClockedTileInputs(implicit val p: Parameters) extends ParameterizedBundle
     with HasExternallyDrivenTileConstants
     with Clocked
 
-trait HasTiles { this: BaseSubsystem =>
+trait HasTiles extends HasCoreMonitorBundles { this: BaseSubsystem =>
   implicit val p: Parameters
   val tiles: Seq[BaseTile]
   protected def tileParams: Seq[TileParams] = tiles.map(_.tileParams)

src/main/scala/subsystem/RocketSubsystem.scala

@@ -51,6 +51,10 @@ trait HasRocketTiles extends HasTiles
     rocket
   }
 
+  def coreMonitorBundles = (rocketTiles map { t =>
+    t.module.core.rocketImpl.coreMonitorBundle
+  }).toList
+
   def getOMRocketCores(resourceBindingsMap: ResourceBindingsMap): Seq[OMComponent] =
     rocketTiles.flatMap(c => c.cpuDevice.getOMComponents(resourceBindingsMap))
 }

src/main/scala/util/CoreMonitor.scala

@@ -0,0 +1,28 @@
+// See LICENSE.Berkeley for license details.
+// See LICENSE.SiFive for license details.
+
+package freechips.rocketchip.util
+
+import chisel3._
+
+// this bundle is used to expose some internal core signals
+// to verification monitors which sample instruction commits
+class CoreMonitorBundle(val xLen: Int) extends Bundle {
+  val hartid = UInt(width = xLen.W)
+  val timer = UInt(width = 32.W)
+  val valid = Bool()
+  val pc = UInt(width = xLen.W)
+  val wrdst = UInt(width = 5.W)
+  val wrdata = UInt(width = xLen.W)
+  val wren = Bool()
+  val rd0src = UInt(width = 5.W)
+  val rd0val = UInt(width = xLen.W)
+  val rd1src = UInt(width = 5.W)
+  val rd1val = UInt(width = xLen.W)
+  val inst = UInt(width = 32.W)
+}
+
+// mark a module that has cores with CoreMonitorBundles
+trait HasCoreMonitorBundles {
+    def coreMonitorBundles: List[CoreMonitorBundle]
+}