Move SeqMems to BigInts and plumb through test mems (#1934)

Enables larger ExtMem sizes with the current TestHarness.

src/main/scala/amba/axi4/SRAM.scala

@@ -31,7 +31,7 @@ class AXI4RAM(
 
   lazy val module = new LazyModuleImp(this) {
     val (in, _) = node.in(0)
-    val (mem, omMem) = makeSinglePortedByteWriteSeqMem(1 << mask.filter(b=>b).size)
+    val (mem, omMem) = makeSinglePortedByteWriteSeqMem(1L << mask.filter(b=>b).size)
     val corrupt = if (wcorrupt) Some(SeqMem(1 << mask.filter(b=>b).size, UInt(width=2))) else None
 
     val r_addr = Cat((mask zip (in.ar.bits.addr >> log2Ceil(beatBytes)).asBools).filter(_._1).map(_._2).reverse)

src/main/scala/diplomacy/SRAM.scala

@@ -31,7 +31,7 @@ abstract class DiplomaticSRAM(
   def mask: List[Boolean] = bigBits(address.mask >> log2Ceil(beatBytes))
 
   // Use single-ported memory with byte-write enable
-  def makeSinglePortedByteWriteSeqMem(size: Int, lanes: Int = beatBytes, bits: Int = 8) = {
+  def makeSinglePortedByteWriteSeqMem(size: BigInt, lanes: Int = beatBytes, bits: Int = 8) = {
     // We require the address range to include an entire beat (for the write mask)
     val mem =  DescribedSRAM(
       name = devName.getOrElse("mem"),

src/main/scala/diplomaticobjectmodel/DiplomaticObjectModelUtils.scala

@@ -181,7 +181,7 @@ object DiplomaticObjectModelAddressing {
 
   def makeOMMemory[T <: Data](
       desc: String,
-      depth: Int,
+      depth: BigInt,
       data: T
     ): OMMemory = {
 

src/main/scala/diplomaticobjectmodel/model/OMMemory.scala

@@ -6,7 +6,7 @@ case class OMMemory(
   description: String,
   addressWidth: Int,
   dataWidth: Int,
-  depth: Int,
+  depth: BigInt,
   writeMaskGranularity: Int,
   _types: Seq[String] = Seq("OMMemory")
 )

src/main/scala/subsystem/Ports.scala

@@ -218,9 +218,10 @@ trait CanHaveSlaveTLPortModuleImp extends LazyModuleImp {
 /** Memory with AXI port for use in elaboratable test harnesses. */
 class SimAXIMem(edge: AXI4EdgeParameters, size: BigInt)(implicit p: Parameters) extends LazyModule {
   val node = AXI4MasterNode(List(edge.master))
-
-  val sram = LazyModule(new AXI4RAM(AddressSet(0, size-1), beatBytes = edge.bundle.dataBits/8))
-  sram.node := AXI4Buffer() := AXI4Fragmenter() := node
+  val srams = AddressSet.misaligned(0, size).map{ aSet => LazyModule(new AXI4RAM(aSet, beatBytes = edge.bundle.dataBits/8))}
+  val xbar = AXI4Xbar()
+  srams.foreach{ s => s.node := AXI4Buffer() := AXI4Fragmenter() := xbar }
+  xbar := node
 
   lazy val module = new LazyModuleImp(this) {
     val io = IO(new Bundle { val axi4 = HeterogeneousBag.fromNode(node.out).flip })

src/main/scala/util/Annotations.scala

@@ -19,7 +19,7 @@ case class SRAMAnnotation(target: Named,
   address_width: Int,
   name: String,
   data_width: Int,
-  depth: Int,
+  depth: BigInt,
   description: String,
   write_mask_granularity: Int) extends SingleTargetAnnotation[Named] {
   def duplicate(n: Named) = this.copy(n)
@@ -109,7 +109,7 @@ object Annotated {
     name: String,
     address_width: Int,
     data_width: Int,
-    depth: Int,
+    depth: BigInt,
     description: String,
     write_mask_granularity: Int): Unit = {
     annotate(new ChiselAnnotation {def toFirrtl: Annotation = SRAMAnnotation(

src/main/scala/util/DescribedSRAM.scala

@@ -16,7 +16,7 @@ object DescribedSRAM {
   def apply[T <: Data](
     name: String,
     desc: String,
-    size: Int, // depth
+    size: BigInt, // depth
     data: T
   ): SyncReadMem[T] = {