Converting systemverilog code to verilog code.
systemverilog2verilog is coverter of systemverilog to verilog.
The script is aimed to preprocess systemverilog for a software (e.g. pyverilog, pyverilog_toolbox, pyeda, ...) that does not correspond to the systemverilog.
- Python (2.7)
git clone https://github.com/fukatani/systemverilog2verilog.git
python sv2v.py systemverilog-file-name.sv
You will get systemverilog-file-name.v.
logic: Convert to reg or wire.
bit: Convert to reg or wire.
byte: Convert to reg [7:0] or wire [7:0] .
enum: Expand to localparam.
e.g.
enum logic [2:0] {PINK,GREEN,YELLOW=5,BLUE} color_e;->
localparam PINK = 'd 0 ;localparam GREEN = 'd 1 ;localparam YELLOW = 'd 5 ;localparam BLUE = 'd 6 ;(.*) port assign: Expand to assignment using port name.
clocking-endcloclking, property-endproperty, sequence-endsequence block: Delete all sentence.
default, assert: Delete line.
always_comb-> always @*
always_latch-> always @*
always_ff-> always
int-> integer
shortint-> reg signed [15:0]
longint-> reg signed [63:0]
'0-> 'd0
'1-> hffff
parameter logic-> parameter
localparam logic-> localparam
function logic-> function
Unimplemented:
interface (may be addressed in the future.)
struct (may be addressed in the future.)
union
Apache License 2.0 (http://www.apache.org/licenses/LICENSE-2.0)
Copyright (C) 2015, Ryosuke Fukatani