More doomed attempts.

revelation/sim.py

@@ -1,6 +1,6 @@
 from pydgin.debug import Debug, pad, pad_hex
 from pydgin.elf import elf_reader
-from pydgin.jit import elidable, JitDriver, set_param, set_user_param
+from pydgin.jit import hint, JitDriver, set_param, set_user_param
 from pydgin.sim import Sim, init_sim
 
 from revelation.argument_parser import cli_parser, DoNotInterpretError
@@ -183,9 +183,9 @@ def run(self):
         coreid = state.coreid  # We save these values so that get_location can
         opcode = 0             # print a more meaningful trace in the JIT log.
         tick_counter = 0       # Number of instructions executed by all cores.
-        max_insts = self.max_insts  # Without this cores don't always halt.
+        max_insts = self.max_insts
         halted_cores, idle_cores = [], []
-        # old_pc = 0
+        old_pc = 0
         self.start_time = time.time()
 
         while len(halted_cores) < self.num_cores:
@@ -227,26 +227,27 @@ def run(self):
             # Update instruction counters.
             tick_counter += 1
             state.num_insts += 1
-            # Halt if we have reached the maximum instruction count or
-            # no more cores are running.
-            if self.max_insts != 0 and state.num_insts >= self.max_insts:
-                print 'Reached the max_insts (%d), exiting.' % self.max_insts
-                break
+            # Halt if we have reached the maximum instruction count.
+            if max_insts != 0 and state.num_insts >= max_insts:
+                print 'Reached the max_insts (%d), exiting.' % max_insts
+                return EXIT_GENERAL_ERROR, tick_counter
             # Check whether state has halted or become idle.
             if not state.running:
+                halted_cores = hint(halted_cores, promote=True)
                 halted_cores.append(core)
                 if len(halted_cores) == self.num_cores:
-                    break
+                    return EXIT_SUCCESS, tick_counter
             elif not state.ACTIVE:
                 idle_cores.append(core)
-            # Switch cores after every instruction. TODO: Switch interval.
+            # Switch cores after every instruction. TODO: Honour switch interval.
             if self.num_cores > 1 and tick_counter % self.switch_interval == 0:
                 while True:
                     core = self.next_core(core)
                     if not (core in halted_cores or core in idle_cores):
                         break
-                    # Idle cores can be reactivated by interrupts.
-                    elif core in idle_cores and self.states[core].rf[reg_map['ILAT']] > 0:
+                    # Idle cores can be made active by interrupts.
+                    elif (core in idle_cores and
+                            self.states[core].rf[reg_map['ILAT']] > 0):
                         idle_cores.remove(core)
                         _service_interrupts(self.states[core])
                         break
@@ -263,7 +264,6 @@ def run(self):
                                              idle_cores=idle_cores,
                                              sim=self,
                                              state=state,)
-        # End of fetch-decode-execute-service interrupts loop.
         return EXIT_SUCCESS, tick_counter
 
     def _print_summary_statistics(self, ticks):
@@ -281,7 +281,7 @@ def _print_summary_statistics(self, ticks):
         if self.collect_times:
             execution_time = self.end_time - self.start_time
             print 'Total execution time: %fs.' % (execution_time)
-            if ticks == -1:
+            if ticks > -1:
                 speed = format_thousands(int(ticks / execution_time))
                 print 'Simulator speed:      %s instructions / second.' % speed