Skip to content

Commit

Permalink
FIX crash in Richards.
Browse files Browse the repository at this point in the history
  • Loading branch information
Sarah Mount committed Aug 7, 2016
1 parent 3690a63 commit 1091e4b
Show file tree
Hide file tree
Showing 2 changed files with 34 additions and 31 deletions.
52 changes: 31 additions & 21 deletions revelation/sim.py
View file
Original file line number Diff line number Diff line change
Expand Up @@ -30,10 +30,10 @@ def new_memory(logger):
return Memory(block_size=2**20, logger=logger)


def get_printable_location(pc, core, coreid, opcode):
def get_printable_location(pc, _, coreid, opcode, halted, idle):
hex_pc = pad_hex(pc)
mnemonic, _ = decode(opcode)
return 'Core ID: 0x%x PC: %s Instruction: %s' % (coreid, hex_pc, mnemonic)
return 'Core index: 0x%x PC: %s Instruction: %s' % (coreid, hex_pc, mnemonic)


class Revelation(Sim):
Expand All @@ -47,9 +47,10 @@ def __init__(self):
self.jit_enabled = True
if self.jit_enabled:
self.jitdriver = JitDriver(
greens = ['pc', 'core', 'coreid', 'opcode'],
reds = ['tick_counter', 'halted_cores', 'idle_cores',
'memory', 'sim', 'state', 'start_time'],
greens=['pc', 'core', 'coreid', 'opcode', 'halted_cores',
'idle_cores'],
reds=['tick_counter', 'max_insts', 'memory', 'sim', 'state',
'start_time'],
get_printable_location=get_printable_location)
self.default_trace_limit = 400000
self.max_insts = 0
Expand Down Expand Up @@ -193,32 +194,34 @@ def run(self):
"""Fetch, decode, execute, service interrupts loop.
Override Sim.run to provide multicore and close the logger on exit.
"""
self = hint(self, promote=True)
memory = hint(self.memory, promote=True) # Cores share the same memory.
coreid = 0 # We save these values so that get_location can print
opcode = 0 # a more meaningful trace in the JIT log.
# We save these coreid and opcode so that get_location can print
# a more meaningful trace in the JIT log.
coreid = self.states[self.core].coreid
opcode = 0
tick_counter = 0 # Number of instructions executed by all cores.
halted_cores, idle_cores = [], []
old_pc = 0
pc = self.states[self.core].fetch_pc()
old_pc = pc
start_time, end_time = time.time(), .0

while True:
while len(halted_cores) != len(self.states):
self.jitdriver.jit_merge_point(pc=self.states[self.core].fetch_pc(),
core=self.core,
coreid=coreid,
opcode=opcode,
tick_counter=tick_counter,
max_insts=self.max_insts,
halted_cores=halted_cores,
idle_cores=idle_cores,
memory=memory,
memory=self.memory,
sim=self,
state=self.states[self.core],
start_time=start_time)
# Fetch PC, decode instruction and execute.
pc = hint(self.states[self.core].fetch_pc(), promote=True)
coreid = hint(self.states[self.core].coreid, promote=True)
pc = self.states[self.core].fetch_pc()
old_pc = pc
opcode = memory.iread(pc, 4, from_core=self.states[self.core].coreid)
opcode = self.memory.iread(pc, 4,
from_core=self.states[self.core].coreid)
try:
instruction, function = self.decode(opcode)
self.pre_execute()
Expand All @@ -230,40 +233,47 @@ def run(self):
(mnemonic, pad_hex(pc)))
print 'Exception message: %s' % error.msg
# Ensure that entry_point() returns correct exit code.
return EXIT_GENERAL_ERROR # pragma: no cover
return EXIT_GENERAL_ERROR # pragma: no cover
# Update instruction counters.
tick_counter += 1
self.states[self.core].num_insts += 1
# Halt if we have reached the maximum instruction count or
# no more cores are running.
if self.max_insts != 0 and self.states[self.core].num_insts >= self.max_insts:
print 'Reached the max_insts (%d), exiting.' % self.max_insts
if (self.max_insts > 0 and
self.states[self.core].num_insts >= self.max_insts):
print ('Core 0x%x has reached the max_insts (%d), exiting.' %
(coreid, self.max_insts))
break
if not self.states[self.core].running:
halted_cores = hint(halted_cores, promote=True)
halted_cores.append(self.core)
if len(halted_cores) == len(self.states):
break
if not self.states[self.core].ACTIVE:
idle_cores = hint(idle_cores, promote=True)
idle_cores.append(self.core)
# Switch cores after every instruction. TODO: Switch interval.
if tick_counter % self.switch_interval == 0 and len(self.states) > 1:
self.core = hint(self.core, promote=True)
while True:
self.core = hint(self.next_core(self.core), promote=True)
self.core = self.next_core(self.core)
if not (self.core in halted_cores or self.core in idle_cores):
break
# Idle cores can be reactivated by interrupts.
elif (self.core in idle_cores and self.fetch_latch() > 0):
idle_cores.remove(self.core)
self._service_interrupts()
coreid = hint(self.states[self.core].coreid, promote=True)
if self.states[self.core].fetch_pc() < old_pc:
self.jitdriver.can_enter_jit(pc=self.states[self.core].fetch_pc(),
core=self.core,
coreid=coreid,
coreid=self.states[self.core].coreid,
opcode=opcode,
tick_counter=tick_counter,
max_insts=self.max_insts,
halted_cores=halted_cores,
idle_cores=idle_cores,
memory=memory,
memory=self.memory,
sim=self,
state=self.states[self.core],
start_time=start_time)
Expand Down
13 changes: 3 additions & 10 deletions revelation/storage.py
View file
Original file line number Diff line number Diff line change
@@ -1,5 +1,5 @@
from pydgin.debug import Debug, pad, pad_hex
from pydgin.jit import elidable, unroll_safe, hint
from pydgin.utils import specialize

from revelation.registers import reg_memory_map

Expand All @@ -15,6 +15,7 @@ def is_register_address(address):
class _BlockMemory(object):
"""32MB block of memory, initialised to zero.
"""
_immutable_fields_ = ['size']

def __init__(self, size=2**10, logger=None):
"""Initialise all memory to zero, as we don't know which memory.
Expand All @@ -23,15 +24,13 @@ def __init__(self, size=2**10, logger=None):
self.data = ['\0'] * size
self.size = len(self.data)

@unroll_safe
def read(self, start_addr, num_bytes):
value = 0
for i in range(num_bytes - 1, -1, -1):
value = value << 8
value = value | ord(self.data[start_addr + i])
return value

@elidable
def iread(self, start_addr, num_bytes):
"""This is instruction read, which is otherwise identical to read. The
only difference is the elidable annotation, which we assume the
Expand All @@ -44,7 +43,6 @@ def iread(self, start_addr, num_bytes):
value = value | ord(self.data[start_addr + i])
return value

@unroll_safe
def write(self, start_addr, num_bytes, value, from_core=0x808):
for i in range(num_bytes):
self.data[start_addr + i] = chr(value & 0xff)
Expand All @@ -68,19 +66,15 @@ def __init__(self, block_size=2**20, logger=None):
def add_block(self, block_addr):
self.block_dict[block_addr] = _BlockMemory(size=self.block_size)

@elidable
def get_block_mem(self, block_addr):
if block_addr not in self.block_dict:
self.add_block(block_addr)
block_mem = self.block_dict[block_addr]
return block_mem

@elidable
def iread(self, start_addr, num_bytes, from_core=0x808):
if is_local_address(start_addr):
start_addr |= (from_core << 20)
start_addr = hint(start_addr, promote=True)
num_bytes = hint(num_bytes, promote=True)
end_addr = start_addr + num_bytes - 1
block_addr = self.block_mask & start_addr
block_mem = self.get_block_mem(block_addr)
Expand All @@ -106,7 +100,6 @@ def read(self, start_addr, num_bytes, from_core=0x808):
if is_local_address(start_addr):
start_addr |= (from_core << 20)
block_addr = self.block_mask & start_addr
block_addr = hint(block_addr, promote=True)
block_mem = self.get_block_mem(block_addr)
masked_addr = 0xfffff & start_addr
value = block_mem.read(start_addr & self.addr_mask, num_bytes)
Expand Down Expand Up @@ -149,7 +142,6 @@ def write(self, start_addr, num_bytes, value, from_core=0x808, quiet=False):
ilat |= 0x10
self.write(coreid_mask | 0xf0428, 4, ilat)
block_addr = self.block_mask & start_addr
block_addr = hint(block_addr, promote=True)
block_mem = self.get_block_mem(block_addr)
block_mem.write(start_addr & self.addr_mask, num_bytes, value)
masked_addr = 0xfffff & start_addr
Expand Down Expand Up @@ -190,6 +182,7 @@ def __getitem__(self, index):
pad_hex(value, len=self.debug_nchars)))
return value

@specialize.argtype(2)
def __setitem__(self, index, value):
if index == 0x65: # COREID register. Read only. Other Read/Write only
return # registers need to be accessed by instructions.
Expand Down

0 comments on commit 1091e4b

Please sign in to comment.