Merge pull request #45 from futurecore/not_implemented_error

Not implemented error

.landscape.yml

@@ -2,4 +2,5 @@ pylint:
   disable:
     - too-many-arguments
     - unused-argument
-
+    - too-many-branches
+    - too-many-boolean-expressions

revelation/execute_branch.py

@@ -1,7 +1,7 @@
 from revelation.condition_codes import condition_passed
+from revelation.registers import reg_map
 from revelation.utils import signed, sext_8, sext_24, trim_32
 
-import revelation.isa
 
 def make_bcond_executor(is16bit):
     def execute_bcond(s, inst):
@@ -18,7 +18,7 @@ def execute_bcond(s, inst):
         cond = inst.cond
         imm = inst.bcond_imm
         if cond == 0b1111:  # Branch and link (BL).
-            s.rf[revelation.isa.reg_map['LR']] = s.pc + (2 if is16bit else 4)
+            s.rf[reg_map['LR']] = s.pc + (2 if is16bit else 4)
         if condition_passed(s, cond):
             offset = (signed(sext_8(imm)) << 1) if is16bit else (signed(sext_24(imm)) << 1)
             s.pc = trim_32(s.pc + offset)

revelation/execute_farith.py

@@ -1,8 +1,8 @@
-from revelation.utils import bits2float, float2bits, get_exponent_as_decimal, is_nan, trim_32
+from revelation.utils import (bits2float, float2bits, get_exponent_as_decimal,
+                              is_nan, trim_32)
+from revelation.registers import reg_map
 from pydgin.utils import signed
 
-import revelation.isa
-
 
 def make_float_executor(is16bit):
     def exec_float(s, inst):
@@ -38,9 +38,9 @@ def exec_float(s, inst):
         s.BVS = s.BVS | s.BV
         # No exceptions for float instruction.
         if s.CTIMER0CONFIG == s.timer_config['FPU VALID'] and not s.BIS:
-            s.rf[revelation.isa.reg_map['CTIMER0']] -= 1
+            s.rf[reg_map['CTIMER0']] -= 1
         if s.CTIMER1CONFIG == s.timer_config['FPU VALID'] and not s.BIS:
-            s.rf[revelation.isa.reg_map['CTIMER1']] -= 1
+            s.rf[reg_map['CTIMER1']] -= 1
         s.debug_flags()
         s.pc += 2 if is16bit else 4
     return exec_float
@@ -88,9 +88,9 @@ def exec_fix(s, inst):
         s.BVS = s.BVS | s.BV
         # FIXME: Find out whether fix generates interrupts.
         if s.CTIMER0CONFIG == s.timer_config['FPU VALID'] and not s.BIS:
-            s.rf[revelation.isa.reg_map['CTIMER0']] -= 1
+            s.rf[reg_map['CTIMER0']] -= 1
         if s.CTIMER1CONFIG == s.timer_config['FPU VALID'] and not s.BIS:
-            s.rf[revelation.isa.reg_map['CTIMER1']] -= 1
+            s.rf[reg_map['CTIMER1']] -= 1
         s.debug_flags()
         s.pc += 2 if is16bit else 4
     return exec_fix
@@ -126,9 +126,9 @@ def exec_fabs(s, inst):
         s.BVS = s.BVS | s.BV
         # Deal with fpu interrupts.
         if s.CTIMER0CONFIG == s.timer_config['FPU VALID'] and not s.BIS:
-            s.rf[revelation.isa.reg_map['CTIMER0']] -= 1  # pragma: no cover
+            s.rf[reg_map['CTIMER0']] -= 1  # pragma: no cover
         if s.CTIMER1CONFIG == s.timer_config['FPU VALID'] and not s.BIS:
-            s.rf[revelation.isa.reg_map['CTIMER1']] -= 1  # pragma: no cover
+            s.rf[reg_map['CTIMER1']] -= 1  # pragma: no cover
         s.debug_flags()
         s.pc += 2 if is16bit else 4
     return exec_fabs
@@ -182,12 +182,12 @@ def farith(s, inst):
             s.BVS = s.BVS | s.BV
             # Deal with fpu interrupts.
             if (s.IEN and s.BIS) or (s.OEN and s.BV) or (s.UEN and s.BUS):
-                s.rf[revelation.isa.reg_map['ILAT']] |= (1 << 1)
+                s.rf[reg_map['ILAT']] |= (1 << 1)
                 s.EXCAUSE = s.exceptions['FPU EXCEPTION']
             if s.CTIMER0CONFIG == s.timer_config['FPU VALID'] and not s.BIS:
-                s.rf[revelation.isa.reg_map['CTIMER0']] -= 1
+                s.rf[reg_map['CTIMER0']] -= 1
             if s.CTIMER1CONFIG == s.timer_config['FPU VALID'] and not s.BIS:
-                s.rf[revelation.isa.reg_map['CTIMER1']] -= 1
+                s.rf[reg_map['CTIMER1']] -= 1
         elif s.ARITHMODE == s.FPU_MODES['SIGNED INTEGER']:
             rd = signed(s.rf[inst.rd])
             rn = signed(s.rf[inst.rn])
@@ -210,9 +210,9 @@ def farith(s, inst):
             # if (RD[30:0] == 0) { BZ=1 } else { BZ=0 }
             s.BZ = True if result == 0 else False
             if s.CTIMER0CONFIG == s.timer_config['IALU VALID']:
-                s.rf[revelation.isa.reg_map['CTIMER0']] -= 1
+                s.rf[reg_map['CTIMER0']] -= 1
             if s.CTIMER1CONFIG == s.timer_config['IALU VALID']:
-                s.rf[revelation.isa.reg_map['CTIMER1']] -= 1
+                s.rf[reg_map['CTIMER1']] -= 1
         s.debug_flags()
         s.pc += 2 if is16bit else 4
     return farith

revelation/execute_interrupt.py

@@ -1,7 +1,7 @@
-from pydgin.misc import FatalError
-
+from revelation.registers import reg_map
 from revelation.utils import trim_32
-import revelation.isa
+
+from pydgin.misc import FatalError, NotImplementedInstError
 
 
 def execute_nop16(s, inst):
@@ -26,15 +26,13 @@ def execute_bkpt16(s, inst):
     GDB and should not be user software. The instruction is included here
     only for the purpose of reference.
     """
-    s.rf[revelation.isa.reg_map['DEBUGSTATUS']] |= 1
-    s.pc += 2
-    s.running = False
+    raise NotImplementedInstError('bkpt instruction not implemented.')
 
 
 def execute_mbkpt16(s, inst):
     """Halts all cores within the group (sets DEBUGSTATUS[0] to 1).
     """
-    raise NotImplementedError('Multicore not implemented.')
+    raise NotImplementedInstError('mbkpt instruction not implemented.')
 
 
 def execute_gie16(s, inst):
@@ -47,8 +45,8 @@ def execute_gie16(s, inst):
         s.pc += 2
         return
     for index in range(10):
-        if not (s.rf[revelation.isa.reg_map['IMASK']] & (1 << index)):
-            s.rf[revelation.isa.reg_map['ILAT']] &= ~(1 << index)
+        if not (s.rf[reg_map['IMASK']] & (1 << index)):
+            s.rf[reg_map['ILAT']] &= ~(1 << index)
     s.GID = 0
     s.pc += 2
 
@@ -67,7 +65,7 @@ def execute_gid16(s, inst):
 def execute_sync16(s, inst):
     """Sets the ILAT[0] of all cores within a work group to 1.
     """
-    raise NotImplementedError('Interrupts not implemented.')
+    raise NotImplementedInstError('sync instruction not implemented.')
 
 
 def execute_rti16(s, inst):
@@ -89,19 +87,19 @@ def execute_rti16(s, inst):
     interrupt_level = s.get_pending_interrupt()
     #     Bit N of IPEND is cleared.
     if interrupt_level >= 0:
-        s.rf[revelation.isa.reg_map['IPEND']] &= ~(1 << interrupt_level)
+        s.rf[reg_map['IPEND']] &= ~(1 << interrupt_level)
     #     The GID bit in STATUS is cleared.
     s.GID = 0
     #     PC is set to IRET.
-    s.pc = s.rf[revelation.isa.reg_map['IRET']]
+    s.pc = s.rf[reg_map['IRET']]
 
 
 def execute_swi16(s, inst):
     # http://blog.alexrp.com/revelation-notes/
     # The architecture has an undocumented SWI instruction which raises a software
     # exception. It sets bit 1 of ILAT and sets the EXCAUSE bits in STATUS to
     # 0b0001 (for Epiphany III) or 0b1110 (for Epiphany IV).
-    s.rf[revelation.isa.reg_map['ILAT']] |= (1 << 1)
+    s.rf[reg_map['ILAT']] |= (1 << 1)
     s.EXCAUSE = s.exceptions['SWI']
     s.pc += 2
 
@@ -200,7 +198,7 @@ def execute_wand16(s, inst):
     """
     STATUS[3] = 1
     """
-    raise NotImplementedError('Multicore not implemented.')
+    raise NotImplementedInstError('wand instruction not implemented.')
 
 
 def execute_unimpl(s, inst):

revelation/execute_jump.py

@@ -1,4 +1,4 @@
-import revelation.isa
+from revelation.registers import reg_map
 from revelation.utils import trim_32
 
 def make_jr_executor(is16bit, save_lr):
@@ -10,6 +10,6 @@ def execute_jr(s, inst):
         if is16bit:
             inst.bits &= 0xffff
         if save_lr:
-            s.rf[revelation.isa.reg_map['LR']] = trim_32(s.pc + (2 if is16bit else 4))
+            s.rf[reg_map['LR']] = trim_32(s.pc + (2 if is16bit else 4))
         s.pc = s.rf[inst.rn]
     return execute_jr

revelation/execute_load_store.py

@@ -1,7 +1,7 @@
-from pydgin.misc import FatalError
-
 from revelation.utils import trim_32
 
+from pydgin.misc import FatalError
+
 
 def execute_ldstrpmd32(s, inst):
     """

revelation/isa.py

@@ -9,79 +9,6 @@
 from pydgin.misc import create_risc_decoder
 
 
-reg_map = {
-    'r0'   :  0,   'r1'   :  1,   'r2'   :  2,   'r3'   :  3,
-    'r4'   :  4,   'r5'   :  5,   'r6'   :  6,   'r7'   :  7,
-    'r8'   :  8,   'r9'   :  9,   'r10'  : 10,   'r11'  : 11,
-    'r12'  : 12,   'r13'  : 13,   'r14'  : 14,   'r15'  : 15,
-    'r16'  : 16,   'r17'  : 17,   'r18'  : 18,   'r19'  : 19,
-    'r20'  : 20,   'r21'  : 21,   'r22'  : 22,   'r23'  : 23,
-    'r24'  : 24,   'r25'  : 25,   'r26'  : 26,   'r27'  : 27,
-    'r28'  : 28,   'r29'  : 29,   'r30'  : 30,   'r31'  : 31,
-    'r32'  : 32,   'r33'  : 33,   'r34'  : 34,   'r35'  : 35,
-    'r36'  : 36,   'r37'  : 37,   'r38'  : 38,   'r39'  : 39,
-    'r40'  : 40,   'r41'  : 41,   'r42'  : 42,   'r43'  : 43,
-    'r44'  : 44,   'r45'  : 45,   'r46'  : 46,   'r47'  : 47,
-    'r48'  : 48,   'r49'  : 49,   'r50'  : 50,   'r51'  : 51,
-    'r52'  : 52,   'r53'  : 53,   'r54'  : 54,   'r55'  : 55,
-    'r56'  : 56,   'r57'  : 57,   'r58'  : 58,   'r59'  : 59,
-    'r60'  : 40,   'r61'  : 61,   'r62'  : 62,   'r63'  : 63,
-    # Synonyms.
-    'SB' : 9,   # Static base
-    'SL' : 10,  # Stack limit
-    'FP' : 11,  # Frame pointer
-    'SP' : 13,  # Stack pointer
-    'LR' : 14,  # Link register
-    # Special registers.
-    'CONFIG'      : 64,  # Core configuration
-    'STATUS'      : 65,  # Core status
-    'pc'          : 66,  # Program counter
-    'DEBUGSTATUS' : 67,  # Debug status
-    'LC'          : 68,  # Hardware counter loop
-    'LS'          : 69,  # Hardware counter start address
-    'LE'          : 70,  # Hardware counter end address
-    'IRET'        : 71,  # Interrupt PC return address
-    'IMASK'       : 72,  # Interrupt mask
-    'ILAT'        : 73,  # Interrupt latch
-    'ILATST'      : 74,  # Alias for setting interrupts
-    'ILATCL'      : 75,  # Alias for clearing interrupts
-    'IPEND'       : 76,  # Interrupt currently in progress
-    'FSTATUS'     : 77,  # Alias for writing to all STATUS bits
-    'DEBUGCMD'    : 78,  # Debug command register
-    'RESETCORE'   : 79,  # Per core software reset
-    # Event timer registers
-    'CTIMER0'     : 80,  # Core timer 0
-    'CTIMER1'     : 81,  # Core timer 1
-    # Process control registers
-    'MEMSTATUS'   : 82,  # Memory protection status
-    'MEMPROTECT'  : 83,  # Memory protection registration
-    # DMA registers
-    'DMA0CONFIG'  : 84,  # DMA channel 0 configuration
-    'DMA0STRIDE'  : 85,  # DMA channel 0 stride
-    'DMA0COUNT'   : 86,  # DMA channel 0 count
-    'DMA0SRCADDR' : 87,  # DMA channel 0 source address
-    'DMA0DSTADDR' : 88,  # DMA channel 0 destination address
-    'DMA0AUTO0'   : 89,  # DMA channel 0 slave lower data
-    'DMA0AUTO1'   : 90,  # DMA channel 0 slave upper data
-    'DMA0STATUS'  : 91,  # DMA channel 0 status
-    'DMA1CONFIG'  : 92,  # DMA channel 1 configuration
-    'DMA1STRIDE'  : 93,  # DMA channel 1 stride
-    'DMA1COUNT'   : 94,  # DMA channel 1 count
-    'DMA1SRCADDR' : 95,  # DMA channel 1 source address
-    'DMA1DSTADDR' : 96,  # DMA channel 1 destination address
-    'DMA1AUTO0'   : 97,  # DMA channel 1 slave lower data
-    'DMA1AUTO1'   : 98,  # DMA channel 1 slave upper data
-    'DMA1STATUS'  : 99,  # DMA channel 1 status
-    # Mesh node control registers
-    'MESHCONFIG'  : 100, # Mesh node configuration
-    'COREID'      : 101, # Processor core ID
-    'MULTICAST'   : 102, # Multicast configuration
-    'CMESHROUTE'  : 103, # cMesh routing configuration, 12 bits
-    'XMESHROUTE'  : 104, # xMesh routing configuration, 12 bits
-    'RMESHROUTE'  : 105, # rMesh routing configuration, 12 bits
-}
-
-
 encodings = [
     # Branch on condition
     ['bcond32',     'xxxxxxxx_xxxxxxxx_xxxxxxxx_xxxx1000'],

revelation/machine.py

@@ -1,9 +1,8 @@
-from revelation.isa import reg_map
+from revelation.registers import LOCAL_PC_ADDRESS, reg_map
 from revelation.storage import MemoryMappedRegisterFile
 
 
 RESET_ADDR = 0
-PC_ADDRESS = 0xf0408
 
 
 class State(object):
@@ -62,15 +61,15 @@ def set_first_core(self, value):
 
     @property
     def pc(self):
-        return self.mem.iread(PC_ADDRESS, 4, from_core=self.coreid)
+        return self.mem.iread(LOCAL_PC_ADDRESS, 4, from_core=self.coreid)
 
     @pc.setter
     def pc(self, value):
-        return self.mem.write(PC_ADDRESS, 4, value, from_core=self.coreid)
+        return self.mem.write(LOCAL_PC_ADDRESS, 4, value, from_core=self.coreid)
 
     def fetch_pc(self):
         # Override method from base class. Needed by Pydgin.
-        return self.mem.iread(PC_ADDRESS, 4, from_core=self.coreid)
+        return self.mem.iread(LOCAL_PC_ADDRESS, 4, from_core=self.coreid)
 
     def get_pending_interrupt(self):
         ipend_highest_bit = -1