Add basic multicore support.

.coveragerc

@@ -1,55 +1,52 @@
 [run]
 omit = revelation/test/*
 data_file = ./.coverage
-source = revelation/
+source = ./revelation/
 
 [report]
 # Regexes for lines to exclude from consideration
 exclude_lines =
     # Have to re-enable the standard pragma
     pragma: no cover
 
-    # Don't complain if tests don't hit defensive assertion code:
-    except subprocess.CalledProcessError as excn:
+    # Don't complain about unimplemented code:
     raise NotImplementedError
 
     # Don't complain if tests take a path which is only used in a test harness:
-    .*we_are_translated.*
     def init_state
     def iread
 
+    # Don't complain about code that only executes when translated.
+    .*we_are_translated.*
+    def get_location
+    _RevelationByteMemory
+
     # Don't complain about every single status bit.
     self._get_nth_bit_of_register
     self._set_nth_bit_of_register
+    def CTRLMODE
 
     # Don't complain about not generating debug output.
     if self.debug.enabled('flags'):
     if self.debug.enabled('rf'):
     if self.debug.enabled('mem'):
     if self.debug.enabled('memcheck'):
+    if self.debug.enabled('trace'):
     if s.debug.enabled('trace'):
+    if self.debug.enabled('syscalls'):
+    if s.debug.enabled('syscalls'):
     if not sparse_storage:
     if self.debug.enabled_flags:
     if self.logger:
+    s.logger.log
     self.logger.log
     self.logger = Logger(LOG_FILENAME)
     self.memory.debug.enabled_flags
     s.debug_flags()
-    self.bounds_check
     print
 
     # Don't complain about invalid memory accesses.
     if addr > self.size:
-    if addr == 0:
-
-
-    # Don't complain about assertions in syscalls -- special code for debuggers
-    inst.t5 == 4
-    inst.t5 == 5
-
-    # Don't complain if non-runnable code isn't run:
-    if 0:
-    if __name__ == .__main__.:
 
     # Don't complain about code that executes if pypy is not on the PYTHONPATH.
     except ImportError:

revelation/argument_parser.py

@@ -0,0 +1,103 @@
+USAGE_TEXT = """Pydgin %s Instruction Set Simulator
+Usage: %s [OPTIONS] [ELFFILE]
+Simulate the execution of ELFFILE.
+
+The following OPTIONS are supported:
+    --help, -h               Show this message and exit
+    --rows, -r ROWS          Number of rows (default: 1)
+    --cols, -c COLS          Number of columns (default: 1)
+    --first-core, -f COREID  Coreid, in hex, of North West core (default: 0x808)
+    --ext-base, -b COREID    Base address of external RAM (default: 0x8e000000)
+    --ext-size, -s SIZE      Size of external RAM in MB (default: 32)
+    --env, -e ENVIRONMENT    Either USER or OPERATING (ignored)
+    --max-insts NUM          Halt after executing NUM instructions
+    --switch N               Switch cores every N instructions (ignored)
+    --time, -t               Print approximate timing information
+    --jit FLAGS              Set flags to tune the JIT (see
+                                 rpython.rlib.jit.PARAMETER_DOCS)
+    --debug,-d FLAGS        Enable debug flags in a comma-separated form. The
+                            following flags are supported:
+                                 trace     pc, decoded instructions
+                                 rf        register file accesses
+                                 mem       memory accesses
+                                 flags     update to CPU flags
+                                 syscalls  system call information
+
+EXAMPLES:
+    $ %s -r 1 -c 2 -f 0x808 program.elf
+    $ %s -r 1 -c 2 --max-insts 20000 program.elf
+    $ %s --time program.elf
+    $ %s --debug trace,rf.mem,flags program.elf
+"""
+
+
+def cli_parser(argv, simulator, debug_enabled):
+    filename_index = 0
+    debug_flags = []
+    jit = ''
+    prev_token = ''
+    tokens_with_args = [ '-b', '--ext-base',
+                         '-c', '--cols',
+                         '-d', '--debug',
+                         '-e', '--env',
+                         '-f', '--first-core',
+                         '--jit',
+                         '--max-insts',
+                         '-r', '--rows',
+                         '-s', '--ext-size',
+                         '--switch',
+                       ]
+    for index, token in enumerate(argv[1:]):
+        if prev_token == '':
+            if token == '--help' or token == '-h':
+                print (USAGE_TEXT % (simulator.arch_name, argv[0], argv[0],
+                                     argv[0], argv[0], argv[0]))
+                raise SystemExit
+            elif token == '--time' or token == '-t':
+                simulator.collect_times = True
+            elif token == '--debug' or token == '-d':
+                prev_token = token
+                if not debug_enabled:
+                    print ('WARNING: debugs are not enabled for this '
+                           'translation. To allow debugs, translate '
+                           'with --debug option.')
+            elif token in tokens_with_args:
+                prev_token = token
+            elif token[:1] == '-':
+                print 'Unknown argument %s' % token
+                raise SystemExit
+            else:
+                filename_index = index + 1
+                break
+        else:
+            if prev_token == '--debug' or prev_token == '-d':
+                debug_flags = token.split(',')
+            elif prev_token == '--env' or prev_token == '-e':
+                if token =='OPERATING':
+                    simulator.user_environment = False
+                elif token == 'USER':
+                    simulator.user_environment = True
+                else:
+                    print ('--env can be OPERATING or USER.')
+                    raise SystemExit
+            elif prev_token == '--ext-base' or prev_token == '-b':
+                simulator.ext_base =int(token, 16)
+            elif prev_token == '--cols' or prev_token == '-c':
+                simulator.cols = int(token)
+            elif prev_token == '--first-core' or prev_token == '-f':
+                simulator.first_core = int(token, 16)
+            elif prev_token == '--jit':  # pragma: no cover
+                jit = token
+            elif prev_token == '--max-insts':
+                simulator.max_insts = int(token)
+            elif prev_token == '--rows' or prev_token == '-r':
+                simulator.rows = int(token)
+            elif prev_token == '--ext-size' or prev_token == '-s':
+                simulator.ext_size = int(token)
+            elif prev_token == '--switch':
+                simulator.switch_interval = int(token)
+            prev_token = ''
+    if filename_index == 0:
+        print 'You must supply a file name'
+        raise SystemExit
+    return argv[filename_index], jit, debug_flags

revelation/elf_loader.py

@@ -0,0 +1,27 @@
+from revelation.storage import is_local_address
+
+from pydgin.elf import elf_reader
+from pydgin.utils import intmask
+
+
+def load_program(fp, mem, alignment=0, is_64bit=False,
+                 coreid=0x808, ext_base=0x8e000000, ext_size=32):
+    """Load an ELF file into an individual core.
+    """
+    elf   = elf_reader(fp, is_64bit=is_64bit)
+    sections   = elf.get_sections()
+    entrypoint = -1
+    coreid_mask = coreid << 20
+    for section in sections:
+        if is_local_address(section.addr):
+            start_addr = coreid_mask | section.addr
+        else:
+            start_addr = section.addr
+        for index, data in enumerate(section.data):
+            mem.write(start_addr + index, 1, ord(data), quiet=True)
+        if section.name == '.text':
+            entrypoint = intmask(section.addr)
+        if section.name == '.data':
+            mem.data_section = section.addr
+    assert entrypoint >= 0
+    return

revelation/execute_bitwise.py

@@ -3,7 +3,6 @@
                               overflow_from_add,
                               overflow_from_sub,
                               reg_or_simm,
-                              signed,
                               trim_32)
 
 #-----------------------------------------------------------------------
@@ -64,7 +63,12 @@ def execute_bit(s, inst):
         elif name == "eor":
             result = rn ^ rm
         elif name == "asr":
-            result = signed(rn) >> (rm & 0x1f)
+            nbit = (rn >> 31) & 1
+            shift = rm & 0x1f
+            signbits = 0
+            if nbit == 1:
+                signbits = 0xffffffff << (32 - shift)
+            result = (rn >> shift) | signbits
         elif name == "lsr":
             result = rn >> (rm & 0x1f)
         elif name == "lsl":

revelation/execute_branch.py

@@ -3,9 +3,6 @@
 
 import revelation.isa
 
-#-----------------------------------------------------------------------
-# bcond16 and bcond32 - branch on condition.
-#-----------------------------------------------------------------------
 def make_bcond_executor(is16bit):
     def execute_bcond(s, inst):
         """

revelation/execute_farith.py

@@ -69,6 +69,10 @@ def farith(s, inst):
             if (s.IEN and s.BIS) or (s.OEN and s.BV) or (s.UEN and s.BUS):
                 s.rf[revelation.isa.reg_map['ILAT']] |= (1 << 1)
                 s.EXCAUSE = s.exceptions['FPU EXCEPTION']
+            if s.CTIMER0CONFIG == s.timer_config['FPU VALID'] and not s.BIS:
+                s.rf[revelation.isa.reg_map['CTIMER0']] -= 1
+            if s.CTIMER1CONFIG == s.timer_config['FPU VALID'] and not s.BIS:
+                s.rf[revelation.isa.reg_map['CTIMER1']] -= 1
         elif s.ARITHMODE == s.FPU_MODES['SIGNED INTEGER']:
             rd = signed(s.rf[inst.rd])
             rn = signed(s.rf[inst.rn])
@@ -90,6 +94,10 @@ def farith(s, inst):
             # s.BN = True if result < 0 else False
             # if (RD[30:0] == 0) { BZ=1 } else { BZ=0 }
             s.BZ = True if result == 0 else False
+            if s.CTIMER0CONFIG == s.timer_config['IALU VALID']:
+                s.rf[revelation.isa.reg_map['CTIMER0']] -= 1
+            if s.CTIMER1CONFIG == s.timer_config['IALU VALID']:
+                s.rf[revelation.isa.reg_map['CTIMER1']] -= 1
         s.debug_flags()
         s.pc += 2 if is16bit else 4
     return farith