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Fix jit benchmark #52

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25 changes: 25 additions & 0 deletions benchmarks/single-core/Makefile
Original file line number Diff line number Diff line change
@@ -0,0 +1,25 @@
SRC=$(wildcard *.c)
ELFS=$(patsubst %.c,%.elf,$(SRC))

ESDK=${EPIPHANY_HOME}
LDF=${ESDK}/bsps/parallella_E16G3_1GB/fast.ldf

CC=e-gcc
CFLAGS=-Wall -Wno-unused -Werror -falign-functions=8
EXTRA_CFLAGS=

LDFLAGS=-T${LDF}
LDLIBS=-le-lib

LIBDIR=${ESDK}/tools/host/lib
INCDIR=${ESDK}/tools/host/include

.PHONY: all clean

all: ${ELFS}

%.elf: %.c
${CC} $< -o $@ ${CFLAGS} ${EXTRA_CFLAGS} -static -L${LIBDIR} -I${INCDIR} ${LDLIBS} ${LDFLAGS}

clean:
-rm -f ${ELFS}
2 changes: 1 addition & 1 deletion benchmarks/single-core/fib_large.c
Original file line number Diff line number Diff line change
Expand Up @@ -5,7 +5,7 @@
#include <stdio.h>
int main() {
unsigned long a = 1, b = 1, i = 0, temp = 0;
for(i = 0; i < 10000; i++) {
for(i = 0; i < 10000000; i++) {
temp = a;
a = b;
b += temp;
Expand Down
Binary file modified benchmarks/single-core/fib_large.elf
100644 → 100755
Binary file not shown.
2 changes: 1 addition & 1 deletion benchmarks/single-core/richards.c
Original file line number Diff line number Diff line change
Expand Up @@ -375,7 +375,7 @@ void append(struct packet *pkt, struct packet *ptr)

int main(void)
{
int reps = 1; /* FIXME: 500 */
int reps = 100; /* FIXME: 500 */
struct packet *wkq = 0;
struct task *tasks[NUM_TASKS];
struct packet *pkts[NUM_PKTS];
Expand Down
Binary file modified benchmarks/single-core/richards.elf
100644 → 100755
Binary file not shown.
2 changes: 1 addition & 1 deletion revelation/argument_parser.py
Original file line number Diff line number Diff line change
Expand Up @@ -27,7 +27,7 @@
$ %s -r 1 -c 2 -f 0x808 program.elf
$ %s -r 1 -c 2 --max-insts 20000 program.elf
$ %s --time program.elf
$ %s --debug trace,rf.mem,flags program.elf
$ %s --debug trace,rf,mem,flags program.elf
"""


Expand Down
1 change: 0 additions & 1 deletion revelation/machine.py
Original file line number Diff line number Diff line change
Expand Up @@ -6,7 +6,6 @@


class State(object):
_virtualizable_ = ['num_insts']

def __init__(self, memory, debug, coreid=0x808, logger=None):
self.rf = MemoryMappedRegisterFile(memory, coreid, logger)
Expand Down
86 changes: 38 additions & 48 deletions revelation/sim.py
Original file line number Diff line number Diff line change
@@ -1,6 +1,6 @@
from pydgin.debug import Debug, pad, pad_hex
from pydgin.elf import elf_reader
from pydgin.jit import elidable, hint, JitDriver, set_param, set_user_param
from pydgin.jit import JitDriver, set_param, set_user_param
from pydgin.sim import Sim, init_sim

from revelation.argument_parser import cli_parser, DoNotInterpretError
Expand All @@ -10,9 +10,9 @@
from revelation.logger import Logger
from revelation.machine import State
from revelation.registers import reg_map
from revelation.storage import Memory
from revelation.utils import (get_coords_from_coreid, get_coreid_from_coords,
zfill)
from revelation.storage import MemoryFactory
from revelation.utils import format_thousands, get_coords_from_coreid
from revelation.utils import get_coreid_from_coords, zfill

from pydgin.misc import FatalError, NotImplementedInstError

Expand All @@ -27,13 +27,13 @@


def new_memory(logger):
return Memory(block_size=2**20, logger=logger)
return MemoryFactory(block_size=2**20, logger=logger)


def get_printable_location(pc, core, coreid, opcode):
def get_printable_location(pc, _, coreid, opcode, halted, idle):
hex_pc = pad_hex(pc)
mnemonic, _ = decode(opcode)
return 'Core ID: 0x%x PC: %s Instruction: %s' % (coreid, hex_pc, mnemonic)
return 'Core index: 0x%x PC: %s Instruction: %s' % (coreid, hex_pc, mnemonic)


class Revelation(Sim):
Expand All @@ -47,24 +47,25 @@ def __init__(self):
self.jit_enabled = True
if self.jit_enabled:
self.jitdriver = JitDriver(
greens = ['pc', 'core', 'coreid', 'opcode'],
reds = ['tick_counter', 'old_pc', 'halted_cores', 'idle_cores',
'memory', 'sim', 'state', 'start_time'],
virtualizables = ['state'],
greens=['pc', 'core', 'coreid', 'opcode', 'halted_cores', 'idle_cores',],
reds=['tick_counter', 'max_insts',
'memory', 'sim', 'state',
'start_time'],
get_printable_location=get_printable_location)
self.default_trace_limit = 400000
self.max_insts = 0
self.logger = None
self.core = 0 # Index of current core (moved after each instruction).
self.core = 0 # Index of current core (moved after each instruction).
self.rows = 1
self.cols = 1
self.first_core = 0x808
self.ext_base = 0x8e000000
self.ext_base = 0x8e000000 # Base address of 'external' memory.
self.ext_size = 32 # MB.
self.switch_interval = 1 # TODO: currently ignored.
self.user_environment = False # TODO: currently ignored.
self.collect_times = False
self.states = []
self.profile = False # Collect timing data BEFORE main loop.
self.states = [] # Cores (revelation.machine.State objects).
self.hardware_loops = []
self.ivt = { # Interrupt vector table.
0 : 0x0, # Sync hardware signal.
Expand All @@ -79,7 +80,6 @@ def __init__(self):
9 : 0x24, # Software-generate user interrupt.
}

@elidable
def next_core(self, core):
return (core + 1) % (self.rows * self.cols)

Expand Down Expand Up @@ -123,14 +123,14 @@ def entry_point(argv):
return entry_point

def decode(self, bits):
mnemonic, exec_fun = decode(bits)
mnemonic, function = decode(bits)
if (self.debug.enabled('trace') and self.logger and
self.states[self.core].is_first_core):
self.logger.log('%s %s %s %s' %
(pad('%x' % self.states[self.core].fetch_pc(), 8, ' ', False),
pad_hex(bits), pad(mnemonic, 12),
pad('%d' % self.states[self.core].num_insts, 8)))
return Instruction(bits, mnemonic), exec_fun
return Instruction(bits, mnemonic), function

def pre_execute(self):
# Check whether or not we are in a hardware loop, and set registers
Expand Down Expand Up @@ -193,45 +193,43 @@ def run(self):
"""Fetch, decode, execute, service interrupts loop.
Override Sim.run to provide multicore and close the logger on exit.
"""
self = hint(self, promote=True)
memory = hint(self.memory, promote=True) # Cores share the same memory.
coreid = 0 # We save these values so that get_location can print
opcode = 0 # a more meaningful trace in the JIT log.
tick_counter = 0 # Number of instructions executed by all cores.
halted_cores, idle_cores = [], []
old_pc = 0
pc = self.states[self.core].fetch_pc()
start_time, end_time = time.time(), .0

while True:
while len(halted_cores) != len(self.states):
self.jitdriver.jit_merge_point(pc=self.states[self.core].fetch_pc(),
core=self.core,
coreid=coreid,
opcode=opcode,
tick_counter=tick_counter,
old_pc=old_pc,
max_insts=self.max_insts,
halted_cores=halted_cores,
idle_cores=idle_cores,
memory=memory,
memory=self.memory,
sim=self,
state=self.states[self.core],
start_time=start_time)
# Fetch PC, decode instruction and execute.
pc = hint(self.states[self.core].fetch_pc(), promote=True)
coreid = hint(self.states[self.core].coreid, promote=True)
old_pc = pc
opcode = memory.iread(pc, 4, from_core=self.states[self.core].coreid)
pc = self.states[self.core].fetch_pc()
self.states[self.core].fetch_pc()
coreid = self.states[self.core].coreid
opcode = self.memory.iread(pc, 4, from_core=self.states[self.core].coreid)
try:
instruction, exec_fun = self.decode(opcode)
instruction, function = self.decode(opcode)
self.pre_execute()
exec_fun(self.states[self.core], instruction)
function(self.states[self.core], instruction)
self.post_execute()
except (FatalError, NotImplementedInstError) as error:
mnemonic, _ = decode(opcode)
print ('Exception in execution of %s (pc: 0x%s), aborting!' %
(mnemonic, pad_hex(pc)))
print 'Exception message: %s' % error.msg
# Ensure that entry_point() returns correct exit code.
return EXIT_GENERAL_ERROR # pragma: no cover
return EXIT_GENERAL_ERROR # pragma: no cover
# Update instruction counters.
tick_counter += 1
self.states[self.core].num_insts += 1
Expand All @@ -249,37 +247,29 @@ def run(self):
# Switch cores after every instruction. TODO: Switch interval.
if tick_counter % self.switch_interval == 0 and len(self.states) > 1:
while True:
self.core = hint(self.next_core(self.core), promote=True)
self.core = self.next_core(self.core)
if not (self.core in halted_cores or self.core in idle_cores):
break
# Idle cores can be reactivated by interrupts.
elif (self.core in idle_cores and self.fetch_latch() > 0):
idle_cores.remove(self.core)
self._service_interrupts()
if self.states[self.core].fetch_pc() < old_pc:
self.jitdriver.can_enter_jit(pc=self.states[self.core].fetch_pc(),
core=self.core,
coreid=coreid,
opcode=opcode,
tick_counter=tick_counter,
old_pc=old_pc,
halted_cores=halted_cores,
idle_cores=idle_cores,
memory=memory,
sim=self,
state=self.states[self.core],
start_time=start_time)
coreid = self.states[self.core].coreid
# End of fetch-decode-execute-service interrupts loop.
if self.collect_times:
end_time = time.time()
print 'Done! Total ticks simulated = %d' % tick_counter
print 'Total ticks simulated = %s.' % format_thousands(tick_counter)
for state in self.states:
row, col = get_coords_from_coreid(state.coreid)
print ('Core %s (%s, %s): STATUS=0x%s, Instructions executed=%d' %
print ('Core %s (%s, %s) STATUS: 0x%s, Instructions executed: %s' %
(hex(state.coreid), zfill(str(row), 2), zfill(str(col), 2),
pad_hex(state.rf[reg_map['STATUS']]), state.num_insts))
pad_hex(state.rf[reg_map['STATUS']]),
format_thousands(state.num_insts)))
if self.collect_times:
print 'Total execution time: %fs' % (end_time - start_time)
execution_time = end_time - start_time
speed = format_thousands(int(tick_counter / execution_time))
print 'Total execution time: %fs.' % (execution_time)
print 'Simulator speed: %s instructions / second.' % speed
if self.logger:
self.logger.close()
return EXIT_SUCCESS
Expand Down
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