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A bidirectional room visitor counter using schematic capture and AHDL on Intel Quartus Prime using an Altera CPLD

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Bidirectional-visitor-counter

A bidirectional room visitor counter using schematic capture and AHDL on Intel Quartus Prime using an Altera CPLD

This bidirectional room visitor counter project uses AHDL and schematic capture to determine the number of people present in a room. It uses IR receiver diodes to track movement and 7 segment displays and LED bar array to display the number in decimal up to 99 and binary up to 128.

IMG-2269

The first version of my bidirectional visitor counter! I initially used two switches on a 4 SPDT Grayhill Switch to test my inputs before switching to the IR receiver and emitter diodes.

Diagrams

rvc falstad simulation image

A circuit simulation using the Falstad Circuit Simulator Applet. You can test the simulation here.

Given the constraints of its implementation on Intel Quartus Prime, circuit adjustments were made for the Falstad simulation.

I directly connected two switches to my D flip flops to test my inputs for both directions. IR receiver and emitter diodes were instead wired and debounced on the breadboard to detect movement and produce clean edges on signals. I also added 8 logic outputs after each D flip flop for the simulation to display the number of people who have passed in either direction separately. This was not done on the breadboard circuit.

image

Block diagram of second version of project on Intel Quartus Prime

The simulation's 7 segment displays automatically use hex digits to count up to FF in hexadecimal (255 in decimal). In reality, the LEDs in each common anode 7-segment display had to be custom coded using AHDL on Quartus in order to display up to 99 in decimal. In addition, JK flip flops are used in the simulation for both frequency counters. In the Quartus block diagram, master slave JK flip flops were used to account for the race around condition and uncontrolled toggling in normal JK flip flops.

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A bidirectional room visitor counter using schematic capture and AHDL on Intel Quartus Prime using an Altera CPLD

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