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video.c
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video.c
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#include "common.h"
#include "palette.h"
// Put temp debug vars here
/*
* Here's how it's calculated according to pcetech.txt :
* The frame counter offset is the substration of VDS and VSW.
* We set it to 14 because that was the default in Temper
* but obviously it should be calculated as such when VDS/VSW change
* as it's done below.
*/
static u32 frame_counter_offset = 14;
#define RGB(r, g, b) ((((r) >> 3) << 11) | (((g) >> 2) << 5) | ((b) >> 3))
//u64 scanline_cycle_counter;
u64 scanline_cycle_counter;
// ARM versions are using this, but it doesn't really hurt to
// have it here like this
u32 sp_storage;
video_debug_mode_enum video_debug_mode = NO_DEBUG;
#ifdef ARM_ARCH
#define scanline_buffer_align __attribute__((aligned(32)))
#else
#define scanline_buffer_align __attribute__((aligned(16)))
#endif
vdc_struct vdc_a;
vdc_struct vdc_b;
vpc_struct vpc;
void update_satb(vdc_struct *vdc);
void vdc_vram_dma_line(vdc_struct *vdc);
/* Gameblabla - Make sure that SDL can adjust the video size here (max should be 512x256) */
static void vdc_update_width(vdc_struct *vdc)
{
s32 screen_width = (vdc->hdw + 1) * 8;
s32 scanline_offset = ((vdc->hsw + vdc->hds) * 8) -
vce.screen_overdraw_offset;
u32 screen_end;
s32 hds_cycles = 0;
if(scanline_offset > (s32)vce.screen_width)
scanline_offset = vce.screen_width;
if(scanline_offset < 0)
{
if(screen_width < 0)
screen_width = 0;
screen_end = screen_width;
vdc->scroll_shift = -scanline_offset;
scanline_offset = 0;
}
else
{
screen_end = screen_width + scanline_offset;
vdc->scroll_shift = 0;
}
if(screen_end >= vce.screen_width)
{
screen_width = vce.screen_width - scanline_offset;
}
else
{
memset(vdc->bg_buffer + 512 + 512 + screen_width, 0,
vce.screen_width - screen_end);
memset(vdc->bg_mask_buffer + ((512 + 512 + screen_width) / 32), 0,
(vce.screen_width - screen_end) / 8);
}
vdc->screen_width = screen_width;
vdc->scanline_offset = scanline_offset;
vdc->screen_end = screen_end;
switch(vce.control & 0x3)
{
case 0:
hds_cycles = ((0x27 - vdc->hdw) * 8) * 4;
if(vdc->hds >= 0x9)
hds_cycles += ((vdc->hds - 0x8) * 8) * 4;
else
if(vdc->hds >= 0x6)
hds_cycles -= 0x15;
break;
case 1:
hds_cycles = ((0x35 - vdc->hdw) * 8) * 3;
if(vdc->hds >= 0xC)
hds_cycles += (((vdc_a.hds - 0xB) * 8) - 0x7) * 3;
else
if(vdc->hds >= 0x7)
hds_cycles -= 0x15;
if(vdc->hds >= 0x12)
hds_cycles += ((vdc->hds - 0x11) * 8) * 4;
break;
case 2:
hds_cycles = ((0x4E - vdc->hdw) * 8) * 2;
if(vdc->hds >= 0x12)
hds_cycles += ((vdc->hds - 0x11) * 8) * 4;
else
if(vdc->hds >= 0x18)
hds_cycles -= 0x15;
break;
case 3:
hds_cycles = ((0x4E - vdc->hdw) * 8) * 2;
if(vdc->hds >= 0x12)
hds_cycles += ((vdc->hds - 0x11) * 8) * 4;
else
if(vdc->hds >= 0x18)
hds_cycles -= 0x15;
break;
}
if(hds_cycles < 0)
hds_cycles = 0;
vdc->hds_cycles = hds_cycles;
update_satb(vdc);
}
#define vdc_interface_functions_builder(_vdc) \
\
u32 vdc_status_##_vdc() \
{ \
memory.io_buffer = _vdc.status; \
irq.status &= ~IRQ_VDC; \
_vdc.status &= ~0x3F; \
\
return memory.io_buffer; \
} \
\
void vdc_register_select_##_vdc(u32 value) \
{ \
_vdc.register_select = value & 0x1F; \
} \
\
u32 vdc_data_read_low_##_vdc() \
{ \
return (_vdc.read_latch & 0xFF); \
} \
\
u32 vdc_data_read_high_##_vdc() \
{ \
u32 read_value = _vdc.read_latch >> 8; \
if(_vdc.register_select == 0x2) \
{ \
_vdc.marr = (_vdc.marr + _vdc.increment_value) & 0xFFFF; \
\
if(_vdc.marr < 0x8000) \
_vdc.read_latch = _vdc.vram[_vdc.marr]; \
} \
\
return read_value; \
} \
\
void vdc_data_write_low_##_vdc(u32 value) \
{ \
switch(_vdc.register_select) \
{ \
case 0x0: \
_vdc.mawr = (_vdc.mawr & 0xFF00) | value; \
break; \
\
case 0x1: \
_vdc.marr = (_vdc.marr & 0xFF00) | value; \
break; \
\
case 0x2: \
_vdc.write_latch = value; \
break; \
\
case 0x5: \
/* control register, low byte */\
/* D7 : 1= Background enable */\
/* D6 : 1= Sprite enable */\
/* D5 : External sync (bit 1) */\
/* D4 : External sync (bit 0) */\
/* D3 : 1= Enable interrupt for vertical blanking */\
/* D2 : 1= Enable interrupt for raster compare */\
/* D1 : 1= Enable interrupt for sprite overflow */\
/* D0 : 1= Enable interrupt for sprite #0 collision */\
_vdc.cr = (_vdc.cr & 0xFF00) | value; \
break; \
\
case 0x6: \
_vdc.rcr = (_vdc.rcr & 0xFF00) | value; \
break; \
\
case 0x7: \
_vdc.bxr = (_vdc.bxr & 0xFF00) | value; \
break; \
\
case 0x8: \
_vdc.byr = (_vdc.byr & 0xFF00) | value; \
_vdc.effective_byr = _vdc.byr; \
break; \
\
case 0x9: \
/* mwr */\
/* D7 : CG mode */\
/* D6 : Virtual screen height */\
/* D5 : Virtual screen width (bit 1) */\
/* D4 : Virtual screen width (bit 0) */\
/* D3 : Sprite dot period (bit 1) */\
/* D2 : Sprite dot period (bit 0) */\
/* D1 : VRAM dot width (bit 1) */\
/* D0 : VRAM dot width (bit 0) */\
_vdc.latched_mwr = value; \
break; \
\
case 0xA: \
_vdc.hsw = value & 0x1F; \
vdc_update_width(&_vdc); \
break; \
\
case 0xB: \
_vdc.hdw = value & 0x7F; \
vdc_update_width(&_vdc); \
break; \
\
case 0xC: \
_vdc.vsw = value & 0x1F; \
break; \
\
case 0xD: \
_vdc.vdw = (_vdc.vdw & 0xFF00) | value; \
break; \
\
case 0xE: \
_vdc.vcr = value; \
break; \
\
case 0xF: \
_vdc.dcr = value; \
break; \
\
case 0x10: \
_vdc.sour = (_vdc.sour & 0xFF00) | value; \
break; \
\
case 0x11: \
_vdc.desr = (_vdc.desr & 0xFF00) | value; \
break; \
\
case 0x12: \
_vdc.lenr = (_vdc.lenr & 0xFF00) | value; \
break; \
\
case 0x13: \
_vdc.satb = (_vdc.satb & 0xFF00) | value; \
_vdc.satb_dma_trigger = 1; \
break; \
\
case 0x3: \
case 0x4: \
break; \
} \
} \
\
void vdc_data_write_high_##_vdc(u32 value) \
{ \
switch(_vdc.register_select) \
{ \
case 0x0: \
_vdc.mawr = (_vdc.mawr & 0xFF) | (value << 8); \
break; \
\
case 0x1: \
_vdc.marr = (_vdc.marr & 0xFF) | (value << 8); \
_vdc.read_latch = _vdc.vram[_vdc.marr]; \
break; \
\
case 0x2: \
{ \
if(_vdc.mawr < 0x8000) \
{ \
u32 write_value = (value << 8) | _vdc.write_latch; \
_vdc.vram[_vdc.mawr] = write_value; \
_vdc.dirty_tiles[_vdc.mawr / 16] = 1; \
_vdc.dirty_patterns[_vdc.mawr / 64] = 1; \
\
if(_vdc.satb_dma_irq_lines) \
{ \
cpu.alert = 1; \
cpu.vdc_stalled = 1; \
} \
} \
\
_vdc.mawr = ((_vdc.mawr + _vdc.increment_value) & 0xFFFF); \
\
break; \
} \
\
case 0x5: \
/* control register, high byte */\
/* D15-D13 : Unused */\
/* D12 : Increment width select (bit 1) */\
/* D11 : Increment width select (bit 0) */\
/* D10 : 1= DRAM refresh enable */\
/* D9 : DISP terminal output mode (bit 1) */\
/* D8 : DISP terminal output mode (bit 0) */\
value &= 0x1F; \
_vdc.cr = (_vdc.cr & 0xFF) | (value << 8); \
switch(value >> 3) \
{ \
case 0x0: \
_vdc.increment_value = 0x01; \
break; \
\
case 0x1: \
_vdc.increment_value = 0x20; \
break; \
\
case 0x2: \
_vdc.increment_value = 0x40; \
break; \
\
case 0x3: \
_vdc.increment_value = 0x80; \
break; \
} \
break; \
\
case 0x6: \
_vdc.rcr = (_vdc.rcr & 0xFF) | ((value & 0x3) << 8); \
break; \
\
case 0x7: \
_vdc.bxr = (_vdc.bxr & 0xFF) | ((value & 0x3) << 8); \
break; \
\
case 0x8: \
{ \
_vdc.byr = (_vdc.byr & 0xFF) | ((value & 0x1) << 8); \
_vdc.effective_byr = _vdc.byr; \
break; \
} \
\
case 0xA: \
_vdc.hds = value & 0x7F; \
vdc_update_width(&_vdc); \
break; \
\
case 0xB: \
_vdc.hde = value & 0x7F; \
break; \
\
case 0xC: \
_vdc.vds = value; \
break; \
\
case 0xD: \
_vdc.vdw = (_vdc.vdw & 0xFF) | ((value & 0x1) << 8); \
break; \
\
case 0x10: \
_vdc.sour = (_vdc.sour & 0xFF) | (value << 8); \
break; \
\
case 0x11: \
_vdc.desr = (_vdc.desr & 0xFF) | (value << 8); \
break; \
\
case 0x12: \
_vdc.lenr = (_vdc.lenr & 0xFF) | (value << 8); \
_vdc.vram_dma_trigger = 1; \
\
/* This is a hack. */\
if(_vdc.burst_mode && ((_vdc.dcr & 0x02) == 0)) \
vdc_vram_dma_line(&_vdc); \
break; \
\
case 0x13: \
_vdc.satb = (_vdc.satb & 0xFF) | (value << 8); \
_vdc.satb_dma_trigger = 1; \
break; \
\
default: \
break; \
} \
} \
#define vdc_select_function_builder(name) \
void name(u32 value) \
{ \
if(vpc.select == VPC_SELECT_VDC_A) \
name##_vdc_a(value); \
else \
name##_vdc_b(value); \
} \
vdc_interface_functions_builder(vdc_a);
vdc_interface_functions_builder(vdc_b);
vdc_select_function_builder(vdc_register_select);
vdc_select_function_builder(vdc_data_write_low);
vdc_select_function_builder(vdc_data_write_high);
void vpc_update_windows(void)
{
s32 first_point = vpc.window1_value;
s32 second_point = vpc.window2_value;
s32 segment_points[3] =
{
0, 0, vce.screen_width
};
s32 previous_segment_point;
u32 i;
u32 segment_statuses[3] =
{
// Window 1 + Window 2
vpc.window_status & 0xF,
// Window 2
(vpc.window_status >> 4) & 0xF,
// No Windows
vpc.window_status >> 12
};
if(first_point > second_point)
{
second_point = first_point;
first_point = vpc.window2_value;
// Set middle segment to window 1.
segment_statuses[1] = (vpc.window_status >> 8) & 0xF;
}
first_point -= 64 + vce.screen_overdraw_offset;
second_point -= 64 + vce.screen_overdraw_offset;
if(first_point < 0)
first_point = 0;
if(second_point < 0)
second_point = 0;
if(first_point > vce.screen_width)
first_point = vce.screen_width;
if(second_point > vce.screen_width)
second_point = vce.screen_width;
segment_points[0] = first_point;
segment_points[1] = second_point;
previous_segment_point = 0;
vpc.window_spans = 0;
for(i = 0; i < 3; i++)
{
if(segment_points[i] != previous_segment_point)
{
vpc.window_span_lengths[vpc.window_spans] =
segment_points[i] - previous_segment_point;
vpc.window_span_status[vpc.window_spans] = segment_statuses[i];
(vpc.window_spans)++;
previous_segment_point = segment_points[i];
}
}
}
u32 vpc_read_window_status_low(void)
{
return vpc.window_status & 0xFF;
}
u32 vpc_read_window_status_high(void)
{
return vpc.window_status >> 8;
}
u32 vpc_read_window1_low(void)
{
return vpc.window1_value & 0xFF;
}
u32 vpc_read_window1_high(void)
{
return vpc.window1_value >> 8;
}
u32 vpc_read_window2_low(void)
{
return vpc.window2_value & 0xFF;
}
u32 vpc_read_window2_high(void)
{
return vpc.window2_value >> 8;
}
void vpc_write_window_status_low(u32 value)
{
vpc.window_status = (vpc.window_status & 0xFF00) | value;
vpc.windows_dirty = 1;
}
void vpc_write_window_status_high(u32 value)
{
vpc.window_status = (vpc.window_status & 0xFF) | (value << 8);
vpc.windows_dirty = 1;
}
void vpc_write_window1_low(u32 value)
{
vpc.window1_value = (vpc.window1_value & 0xFF00) | value;
vpc.windows_dirty = 1;
}
void vpc_write_window1_high(u32 value)
{
vpc.window1_value = (vpc.window1_value & 0xFF) | (value << 8);
vpc.windows_dirty = 1;
}
void vpc_write_window2_low(u32 value)
{
vpc.window2_value = (vpc.window2_value & 0xFF00) | value;
vpc.windows_dirty = 1;
}
void vpc_write_window2_high(u32 value)
{
vpc.window2_value = (vpc.window2_value & 0xFF) | (value << 8);
vpc.windows_dirty = 1;
}
void vpc_select(u32 value)
{
vpc.select = value & 0x1;
}
void initialize_vdc(vdc_struct *vdc)
{
memset(vdc->bg_buffer, 0, sizeof(vdc->bg_buffer));
memset(vdc->bg_mask_buffer, 0, sizeof(vdc->bg_mask_buffer));
}
void reset_vdc(vdc_struct *vdc)
{
u32 i;
vdc->status = 0;
vdc->register_select = 0;
vdc->mawr = 0;
vdc->marr = 0;
vdc->cr = 0;
vdc->rcr = 0;
vdc->mwr = 0;
vdc->bxr = 0;
vdc->byr = 0;
vdc->dcr = 0;
vdc->sour = 0;
vdc->desr = 0;
vdc->lenr = 0;
vdc->satb = 0;
vdc->write_latch = 0xFF;
vdc->read_latch = 0xFF;
vdc->raster_line = 0;
vdc->effective_byr = 0;
vdc->increment_value = 1;
vdc->satb_dma_trigger = 0;
vdc->satb_dma_irq_lines = 0;
vdc->vram_dma_trigger = 0;
vdc->vram_dma_irq_lines = 0;
vdc->hsw = 0x1F;
vdc->hds = 0x00;
vdc->hdw = 0x7F;
vdc->hde = 0x00;
vdc->vsw = 0x02;
vdc->vds = 0x0F;
vdc->vdw = 0xFF;
// pcetech.txt says max should be 0xC0
vdc->vcr = 0xFF;
vdc->display_counter = 0;
vdc->burst_mode = 0;
memset(vdc->dirty_tiles, 0, sizeof(vdc->dirty_tiles));
memset(vdc->dirty_patterns, 0, sizeof(vdc->dirty_patterns));
memset(vdc->vram, 0, 64 * 1024);
memset(vdc->tile_cache, 0, sizeof(vdc->tile_cache));
memset(vdc->pattern_cache, 0, sizeof(vdc->pattern_cache));
memset(vdc->tile_cache_transparency_mask, 0,
sizeof(vdc->tile_cache_transparency_mask));
memset(vdc->pattern_cache_transparency_mask, 0,
sizeof(vdc->pattern_cache_transparency_mask));
memset(vdc->sat, 0xFF, 64 * 8);
update_satb(vdc);
for(i = 0; i < 243; i++)
{
vdc->sat_cache.lines[i].num_active = 0;
}
vdc_update_width(vdc);
}
vce_struct vce;
/* We might need an 8bpp renderer but most of Temper assumes a 16bpp buffer... */
void initialize_palette_convert()
{
/* Requires float support. As such, this may not be appropriate for low end hardware. (despite the increased filesize) */
#ifdef OLD_PALETTE_INACCURATE
s32 color, r, g, b;
s32 y, ry, by;
//double f_y, f_ry, f_by;
//double f_r, f_g, f_b;
float f_y, f_ry, f_by;
float f_r, f_g, f_b;
for(color = 0; color < 512; color++)
{
g = ((color >> 6) & 0x7);
r = ((color >> 3) & 0x7);
b = (color & 0x7);
y = (r * 133) + (g * 261) + (b * 49);
ry = (r * 214) + (g * -180) + (b * -34);
by = (r * -72) + (g * -142) + (b * 214);
y += 50;
if(ry < 0)
ry -= 50;
else
ry += 50;
if(by < 0)
by -= 50;
else
by += 50;
y /= 100;
ry /= 100;
by /= 100;
f_y = y / 31.0f;
f_ry = (ry / 15.0f) * 0.701f * 0.75f;
f_by = (by / 15.0f) * 0.886f * 0.75f;
f_r = f_y + f_ry;
f_g = f_y - ((0.114f / 0.587f) * f_by) - ((0.229f / 0.587f) * f_ry);
f_b = f_y + f_by;
r = (u32)(floor(f_r * 31.0f) + 0.5f);
b = (u32)(floor(f_b * 31.0f) + 0.5f);
if(r < 0)
r = 0;
if(b < 0)
b = 0;
if(r > 31)
r = 31;
if(b > 31)
b = 31;
#ifdef COLOR_RGB_555
g = (u32)(floor(f_g * 31.0f) + 0.5f);
if(g > 31)
g = 31;
#else
g = (u32)(floor(f_g * 63.0f) + 0.5f);
if(g > 63)
g = 63;
#endif
if(g < 0)
g = 0;
#ifdef COLOR_BGR_565
palette_convert[color] = (b << 11) | (g << 5) | r;
#endif
#ifdef COLOR_RGB_565
palette_convert[color] = (r << 11) | (g << 5) | b;
#endif
#ifdef COLOR_RGB_555
palette_convert[color] = (r << 10) | (g << 5) | b;
#endif
}
#endif
}
void vce_control_write(u32 value)
{
vce.control = value;
// Pixel clock mode
switch(value & 0x3)
{
case 0:
vce.screen_width = 256;
vce.screen_overdraw_offset = 32;
vce.scanline_cycles = 1364;
break;
case 1:
// This is cut off, but fits best into all target resolutions, so we're
// going with it for now.
vce.screen_width = 320;
vce.screen_overdraw_offset = 64;
vce.scanline_cycles = 1365;
break;
case 2:
vce.screen_width = 512;
vce.screen_overdraw_offset = 104;
vce.scanline_cycles = 1364;
break;
case 3:
vce.screen_width = 512;
vce.screen_overdraw_offset = 104;
vce.scanline_cycles = 1364;
if(value & 0x4)
vce.scanline_cycles += 2;
break;
}
#ifdef IPU_SCALING
vce.screen_center_offset = 0;
#else
vce.screen_center_offset = (RESOLUTION_WIDTH - vce.screen_width) / 2;
#endif
vdc_update_width(&vdc_a);
if(config.sgx_mode)
vdc_update_width(&vdc_b);
// This frame_counter_offset thing really doesn't work at all
#ifdef IPU_SCALING
u32 height;
frame_counter_offset = (vdc_a.vds + vdc_a.vsw);
// HACK
if (vdc_a.vds > 0x80) frame_counter_offset = 20;
#ifdef CRC_CHECK
if (height_crop > 0)
{
height = height_crop;
frame_counter_offset = framecounter_force;
}
else
#endif
{
/* Gameblabla : How is it exactly done ? Get more info about it. TODO */
switch(vdc_a.vds)
{
// case 0xF:
default:
height = 240;
break;
case 0xE:
case 0x17:
height = 224;
break;
case 0x25:
height = 192;
break;
}
}
set_screen_resolution(vce.screen_width, height, 1);
#endif
// Interlace bit determines how many scanlines there are.
if(value & 0x4)
vce.num_lines = 263;
else
vce.num_lines = 262;
}
void vce_address_write_low(u32 value)
{
vce.palette_offset = (vce.palette_offset & 0xFF00) | value;
}
void vce_address_write_high(u32 value)
{
vce.palette_offset = (vce.palette_offset & 0xFF) | ((value & 0x1) << 8);
}
u32 vce_data_read_low()
{
return vce.palette[vce.palette_offset] & 0xFF;
}
u32 vce_data_read_high()
{
u32 palette_entry = (vce.palette[vce.palette_offset] >> 8) | 0xFE;
vce.palette_offset = (vce.palette_offset + 1) & 0x1FF;
return palette_entry;
}
void vce_data_write_low(u32 value)
{
u16 palette_entry = vce.palette[vce.palette_offset];
palette_entry = (palette_entry & 0xFF00) | value;
vce.palette[vce.palette_offset] = palette_entry;
if(((vce.palette_offset & 0x0F) == 0) && (vce.palette_offset < 0x100))
{
if(vce.palette_offset == 0)
{
u32 i;
u16 *palette_ptr = vce.palette_cache +
(vce.palette_offset & 0x100);
palette_entry = palette_convert[palette_entry];
for(i = 0; i < 16; i++)
{
*palette_ptr = palette_entry;
palette_ptr += 16;
}
}
}
else
{
if(vce.palette_offset == 0x100)
vce.clear_edges = 1;
vce.palette_cache[vce.palette_offset] =
palette_convert[palette_entry];
}
}
void vce_data_write_high(u32 value)
{
u16 palette_entry = vce.palette[vce.palette_offset];
palette_entry = (palette_entry & 0xFF) | ((value & 0x1) << 8);
vce.palette[vce.palette_offset] = palette_entry;
if(((vce.palette_offset & 0x0F) == 0) && (vce.palette_offset < 0x100))
{
if(vce.palette_offset == 0)
{
u32 i;
u16 *palette_ptr = vce.palette_cache +
(vce.palette_offset & 0x100);
palette_entry = palette_convert[palette_entry];
for(i = 0; i < 16; i++)
{
*palette_ptr = palette_entry;
palette_ptr += 16;
}
}
}
else
{
vce.palette_cache[vce.palette_offset] =
palette_convert[palette_entry];
}
vce.palette_offset = (vce.palette_offset + 1) & 0x1FF;
}
void reset_vce()
{
u32 i;
vce.palette_offset = 0;
vce.num_lines = 262;
vce.frame_counter = 0;
vce_control_write(0);
memset(vce.palette, 0, 512 * 2);
memset(vce.palette_cache, 0, 512 * 2);
for(i = 0; i < 242; i++)
{
vce.pixels_drawn[i] = RESOLUTION_WIDTH;
}
vce.frames_rendered = 0;
}
void reset_vpc()
{
vpc.window_status = 0x1111;
vpc.window1_value = 0;
vpc.window2_value = 0;
vpc.select = 0;
vpc.windows_dirty = 1;
}
void initialize_vce()
{
}
void initialize_vpc()
{
}
void reset_video()
{
reset_vdc(&vdc_a);
if(config.sgx_mode)
{
reset_vdc(&vdc_b);
reset_vpc();
}
reset_vce();
}
void initialize_video()
{
initialize_palette_convert();
initialize_vdc(&vdc_a);
initialize_vdc(&vdc_b);
initialize_vce();
initialize_vpc();
set_screen_resolution(RESOLUTION_WIDTH, RESOLUTION_HEIGHT, 1);
clear_screen();
}
void cache_tile(vdc_struct *vdc, u32 tile_number)
{
// Tiles consist of 2 16byte half-tiles contiguously in VRAM.
// Each half-tile consists of 2 planes interleaved in 8 rows.
// The tile cache consists of 64 8-bit pixels consecutively.
u16 *vram_offset = vdc->vram + (tile_number * 16);
u8 *tile_cache_offset = vdc->tile_cache + (tile_number * 64);
u8 *tile_cache_transparency_mask_offset =
vdc->tile_cache_transparency_mask + (tile_number * 8);
u32 transparency_mask;
u32 plane_row_a, plane_row_b;
u32 x, y;
for(y = 0; y < 8; y++)
{
plane_row_a = vram_offset[y];
plane_row_b = vram_offset[y + 8];
// 16bits -> 8 pixels (32bits packed 4bpp)
for(x = 0; x < 8; x++)
{
tile_cache_offset[x] =
((plane_row_a >> (7 - x)) & 0x1) |
(((plane_row_a >> ((7 - x) + 8)) & 0x1) << 1) |
(((plane_row_b >> (7 - x)) & 0x1) << 2) |
(((plane_row_b >> ((7 - x) + 8)) & 0x1) << 3);
}
transparency_mask =
plane_row_a | (plane_row_a >> 8) | plane_row_b | (plane_row_b >> 8);