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CPU IPC is low: eradicate fastram wait-state on read #32

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gardners opened this issue Feb 22, 2014 · 1 comment
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CPU IPC is low: eradicate fastram wait-state on read #32

gardners opened this issue Feb 22, 2014 · 1 comment

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@gardners
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If we put the CPU-side interface of the fastram onto the pixel clock, instead of the cpuclock, reads will occur in less than one CPU cycle, so the waitstate can be removed. The question is whether it will introduce any write glitches, which obviously we cannot tolerate.
gardners added a commit that referenced this issue Feb 22, 2014
@gardners
try removing fastram read waitstate by pushing fastram CPU-side
0183742 
to pixelclock. Issue #32.
@gardners
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This seems to work.

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