APU channel 3 docs should refer to channel 3 registers (#517)

* low 8 bits of channel 3 period are in NR33, not NR13

* CH1->CH3 copypaste error in trigger field description too

src/Audio_Registers.md

@@ -295,7 +295,7 @@ Period changes (written to `NR33` or `NR34`) only take effect after the followin
   "NR34" 7:"Trigger" 6:"Length enable" 2-0:"Period"
 }}
 
-- **Trigger** (*Write-only*): Writing any value to `NR14` with this bit set [triggers](<#Triggering>) the channel.
+- **Trigger** (*Write-only*): Writing any value to `NR34` with this bit set [triggers](<#Triggering>) the channel.
 
   :::warning RETRIGGERING CAUTION
 
@@ -310,7 +310,7 @@ Period changes (written to `NR33` or `NR34`) only take effect after the followin
 
   :::
 - **[Length](<#Length timer>) enable** (*Read/Write*): Takes effect immediately upon writing to this register.
-- **Period** (*Write-only*): The upper 3 bits of the period value; the lower 8 bits are stored in [`NR13`](<#FF13 — NR13: Channel 1 period low \[write-only\]>).
+- **Period** (*Write-only*): The upper 3 bits of the period value; the lower 8 bits are stored in [`NR33`](<#FF1D — NR33: Channel 3 period low \[write-only\]>).
 
 ### FF30–FF3F — Wave pattern RAM