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RISC-V: Fix attributes bug configuration of ternary instructions
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This patch fixes the following FAILs:

Running target riscv-sim/-march=rv64gcv/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-preference=fixed-vlmax
FAIL: gcc.c-torture/execute/pr68532.c   -O0  execution test
FAIL: gcc.c-torture/execute/pr68532.c   -O1  execution test
FAIL: gcc.c-torture/execute/pr68532.c   -O2  execution test
FAIL: gcc.c-torture/execute/pr68532.c   -O3 -fomit-frame-pointer -funroll-loops -fpeel-loops -ftracer -finline-functions  execution test
FAIL: gcc.c-torture/execute/pr68532.c   -O3 -g  execution test
FAIL: gcc.c-torture/execute/pr68532.c   -Os  execution test
FAIL: gcc.c-torture/execute/pr68532.c   -O2 -flto -fno-use-linker-plugin -flto-partition=none  execution test

Running target riscv-sim/-march=rv64gcv/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m2/--param=riscv-autovec-preference=fixed-vlmax
FAIL: gcc.dg/vect/pr60196-1.c execution test
FAIL: gcc.dg/vect/pr60196-1.c -flto -ffat-lto-objects execution test

Running target riscv-sim/-march=rv64gcv/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-preference=fixed-vlmax
FAIL: gcc.dg/vect/pr60196-1.c execution test
FAIL: gcc.dg/vect/pr60196-1.c -flto -ffat-lto-objects execution test

Running target riscv-sim/-march=rv64gcv_zvl256b/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-preference=fixed-vlmax
FAIL: gcc.dg/vect/pr60196-1.c execution test
FAIL: gcc.dg/vect/pr60196-1.c -flto -ffat-lto-objects execution test

The root cause is attributes of ternary intructions are incorrect which cause AVL prop PASS and VSETVL PASS behave
incorrectly.

Tested no regression and committed.

	PR target/113393

gcc/ChangeLog:

	* config/riscv/vector.md: Fix ternary attributes.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/autovec/pr113393-1.c: New test.
	* gcc.target/riscv/rvv/autovec/pr113393-2.c: New test.
	* gcc.target/riscv/rvv/autovec/pr113393-3.c: New test.
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zhongjuzhe authored and Incarnation-p-lee committed Jan 15, 2024
1 parent 65678b2 commit 0627d1f
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Showing 4 changed files with 79 additions and 21 deletions.
42 changes: 21 additions & 21 deletions gcc/config/riscv/vector.md
Original file line number Diff line number Diff line change
Expand Up @@ -715,7 +715,7 @@
(const_int 1)

(eq_attr "type" "vimuladd,vfmuladd")
(const_int 5)]
(const_int 2)]
(const_int INVALID_ATTRIBUTE)))

;; The index of operand[] represents the machine mode of the instruction.
Expand Down Expand Up @@ -5308,7 +5308,7 @@
vmv.v.v\t%0,%2\;vmadd.vv\t%0,%3,%4%p1"
[(set_attr "type" "vimuladd")
(set_attr "mode" "<MODE>")
(set_attr "merge_op_idx" "4")
(set_attr "merge_op_idx" "2")
(set_attr "vl_op_idx" "5")
(set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
(set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
Expand Down Expand Up @@ -5339,7 +5339,7 @@
vmv.v.v\t%0,%4\;vmacc.vv\t%0,%2,%3%p1"
[(set_attr "type" "vimuladd")
(set_attr "mode" "<MODE>")
(set_attr "merge_op_idx" "2")
(set_attr "merge_op_idx" "4")
(set_attr "vl_op_idx" "5")
(set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
(set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
Expand Down Expand Up @@ -5392,7 +5392,7 @@
vmv.v.v\t%0,%3\;vmadd.vx\t%0,%2,%4%p1"
[(set_attr "type" "vimuladd")
(set_attr "mode" "<MODE>")
(set_attr "merge_op_idx" "4")
(set_attr "merge_op_idx" "3")
(set_attr "vl_op_idx" "5")
(set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
(set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
Expand Down Expand Up @@ -5424,7 +5424,7 @@
vmv.v.v\t%0,%4\;vmacc.vx\t%0,%2,%3%p1"
[(set_attr "type" "vimuladd")
(set_attr "mode" "<MODE>")
(set_attr "merge_op_idx" "2")
(set_attr "merge_op_idx" "4")
(set_attr "vl_op_idx" "5")
(set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
(set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
Expand Down Expand Up @@ -5492,7 +5492,7 @@
vmv.v.v\t%0,%2\;vmadd.vx\t%0,%2,%4%p1"
[(set_attr "type" "vimuladd")
(set_attr "mode" "<MODE>")
(set_attr "merge_op_idx" "4")
(set_attr "merge_op_idx" "3")
(set_attr "vl_op_idx" "5")
(set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
(set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
Expand Down Expand Up @@ -5525,7 +5525,7 @@
vmv.v.v\t%0,%4\;vmacc.vx\t%0,%2,%3%p1"
[(set_attr "type" "vimuladd")
(set_attr "mode" "<MODE>")
(set_attr "merge_op_idx" "2")
(set_attr "merge_op_idx" "4")
(set_attr "vl_op_idx" "5")
(set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
(set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
Expand Down Expand Up @@ -5606,7 +5606,7 @@
vmv.v.v\t%0,%2\;vnmsub.vv\t%0,%3,%4%p1"
[(set_attr "type" "vimuladd")
(set_attr "mode" "<MODE>")
(set_attr "merge_op_idx" "4")
(set_attr "merge_op_idx" "2")
(set_attr "vl_op_idx" "5")
(set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
(set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
Expand Down Expand Up @@ -5637,7 +5637,7 @@
vmv.v.v\t%0,%4\;vnmsac.vv\t%0,%2,%3%p1"
[(set_attr "type" "vimuladd")
(set_attr "mode" "<MODE>")
(set_attr "merge_op_idx" "2")
(set_attr "merge_op_idx" "4")
(set_attr "vl_op_idx" "5")
(set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
(set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
Expand Down Expand Up @@ -5690,7 +5690,7 @@
vmv.v.v\t%0,%3\;vnmsub.vx\t%0,%2,%4%p1"
[(set_attr "type" "vimuladd")
(set_attr "mode" "<MODE>")
(set_attr "merge_op_idx" "4")
(set_attr "merge_op_idx" "3")
(set_attr "vl_op_idx" "5")
(set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
(set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
Expand Down Expand Up @@ -5722,7 +5722,7 @@
vmv.v.v\t%0,%4\;vnmsac.vx\t%0,%2,%3%p1"
[(set_attr "type" "vimuladd")
(set_attr "mode" "<MODE>")
(set_attr "merge_op_idx" "2")
(set_attr "merge_op_idx" "4")
(set_attr "vl_op_idx" "5")
(set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
(set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
Expand Down Expand Up @@ -5790,7 +5790,7 @@
vmv.v.v\t%0,%3\;vnmsub.vx\t%0,%2,%4%p1"
[(set_attr "type" "vimuladd")
(set_attr "mode" "<MODE>")
(set_attr "merge_op_idx" "4")
(set_attr "merge_op_idx" "3")
(set_attr "vl_op_idx" "5")
(set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
(set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
Expand Down Expand Up @@ -5823,7 +5823,7 @@
vmv.v.v\t%0,%4\;vnmsac.vx\t%0,%2,%3%p1"
[(set_attr "type" "vimuladd")
(set_attr "mode" "<MODE>")
(set_attr "merge_op_idx" "2")
(set_attr "merge_op_idx" "4")
(set_attr "vl_op_idx" "5")
(set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
(set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
Expand Down Expand Up @@ -6516,7 +6516,7 @@
vmv.v.v\t%0,%2\;vf<madd_msub>.vv\t%0,%3,%4%p1"
[(set_attr "type" "vfmuladd")
(set_attr "mode" "<MODE>")
(set_attr "merge_op_idx" "4")
(set_attr "merge_op_idx" "2")
(set_attr "vl_op_idx" "5")
(set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
(set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
Expand Down Expand Up @@ -6551,7 +6551,7 @@
vmv.v.v\t%0,%4\;vf<macc_msac>.vv\t%0,%2,%3%p1"
[(set_attr "type" "vfmuladd")
(set_attr "mode" "<MODE>")
(set_attr "merge_op_idx" "2")
(set_attr "merge_op_idx" "4")
(set_attr "vl_op_idx" "5")
(set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
(set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
Expand Down Expand Up @@ -6610,7 +6610,7 @@
vmv.v.v\t%0,%3\;vf<madd_msub>.vf\t%0,%2,%4%p1"
[(set_attr "type" "vfmuladd")
(set_attr "mode" "<MODE>")
(set_attr "merge_op_idx" "4")
(set_attr "merge_op_idx" "3")
(set_attr "vl_op_idx" "5")
(set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
(set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
Expand Down Expand Up @@ -6646,7 +6646,7 @@
vmv.v.v\t%0,%4\;vf<macc_msac>.vf\t%0,%2,%3%p1"
[(set_attr "type" "vfmuladd")
(set_attr "mode" "<MODE>")
(set_attr "merge_op_idx" "2")
(set_attr "merge_op_idx" "4")
(set_attr "vl_op_idx" "5")
(set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
(set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
Expand Down Expand Up @@ -6740,7 +6740,7 @@
vmv.v.v\t%0,%2\;vf<nmsub_nmadd>.vv\t%0,%3,%4%p1"
[(set_attr "type" "vfmuladd")
(set_attr "mode" "<MODE>")
(set_attr "merge_op_idx" "4")
(set_attr "merge_op_idx" "2")
(set_attr "vl_op_idx" "5")
(set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
(set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
Expand Down Expand Up @@ -6776,7 +6776,7 @@
vmv.v.v\t%0,%4\;vf<nmsac_nmacc>.vv\t%0,%2,%3%p1"
[(set_attr "type" "vfmuladd")
(set_attr "mode" "<MODE>")
(set_attr "merge_op_idx" "2")
(set_attr "merge_op_idx" "4")
(set_attr "vl_op_idx" "5")
(set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
(set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
Expand Down Expand Up @@ -6837,7 +6837,7 @@
vmv.v.v\t%0,%3\;vf<nmsub_nmadd>.vf\t%0,%2,%4%p1"
[(set_attr "type" "vfmuladd")
(set_attr "mode" "<MODE>")
(set_attr "merge_op_idx" "4")
(set_attr "merge_op_idx" "3")
(set_attr "vl_op_idx" "5")
(set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
(set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
Expand Down Expand Up @@ -6874,7 +6874,7 @@
vmv.v.v\t%0,%4\;vf<nmsac_nmacc>.vf\t%0,%2,%3%p1"
[(set_attr "type" "vfmuladd")
(set_attr "mode" "<MODE>")
(set_attr "merge_op_idx" "2")
(set_attr "merge_op_idx" "4")
(set_attr "vl_op_idx" "5")
(set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
(set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
Expand Down
24 changes: 24 additions & 0 deletions gcc/testsuite/gcc.target/riscv/rvv/autovec/pr113393-1.c
Original file line number Diff line number Diff line change
@@ -0,0 +1,24 @@
/* { dg-do run } */
/* { dg-options "-O3 --param=riscv-autovec-preference=fixed-vlmax" } */
/* { dg-require-effective-target riscv_v } */

#define SIZE 128
unsigned short _Alignas (16) in[SIZE];

__attribute__ ((noinline)) int
test (unsigned short sum, unsigned short *in, int x)
{
for (int j = 0; j < SIZE; j += 8)
sum += in[j] * x;
return sum;
}

int
main ()
{
for (int i = 0; i < SIZE; i++)
in[i] = i;
if (test (0, in, 1) != 960)
__builtin_abort ();
return 0;
}
29 changes: 29 additions & 0 deletions gcc/testsuite/gcc.target/riscv/rvv/autovec/pr113393-2.c
Original file line number Diff line number Diff line change
@@ -0,0 +1,29 @@
/* { dg-do run } */
/* { dg-options "-O3 --param=riscv-autovec-preference=fixed-vlmax --param=riscv-autovec-lmul=m2" } */
/* { dg-require-effective-target riscv_v } */

__attribute__((noinline, noclone)) static int
bar (const short *a, int len)
{
int x;
int x1 = 0;

for (x = 0; x < len; x++)
x1 += x * a[x];
return x1;
}

__attribute__((noinline, noclone)) void
foo (void)
{
short stuff[9] = {1, 1, 1, 1, 1, 1, 1, 1, 1 };
if (bar (stuff, 9) != 36)
__builtin_abort ();
}

int
main ()
{
foo ();
return 0;
}
5 changes: 5 additions & 0 deletions gcc/testsuite/gcc.target/riscv/rvv/autovec/pr113393-3.c
Original file line number Diff line number Diff line change
@@ -0,0 +1,5 @@
/* { dg-do run } */
/* { dg-options "-O3 --param=riscv-autovec-preference=fixed-vlmax" } */
/* { dg-require-effective-target riscv_v } */

#include "pr113393-2.c"

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