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RISC-V: T-HEAD: Add support for the XTheadInt ISA extension
The XTheadInt ISA extension provides the following instructions to accelerate interrupt processing: * th.ipush * th.ipop Ref: https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.3.0/xthead-2023-11-10-2.3.0.pdf gcc/ChangeLog: * config/riscv/riscv-protos.h (th_int_get_mask): New prototype. (th_int_get_save_adjustment): Likewise. (th_int_adjust_cfi_prologue): Likewise. * config/riscv/riscv.cc (BITSET_P): Moved away from here. (TH_INT_INTERRUPT): New macro. (riscv_expand_prologue): Add the processing of XTheadInt. (riscv_expand_epilogue): Likewise. * config/riscv/riscv.h (BITSET_P): Moved to here. * config/riscv/riscv.md: New unspec. * config/riscv/thead.cc (th_int_get_mask): New function. (th_int_get_save_adjustment): Likewise. (th_int_adjust_cfi_prologue): Likewise. * config/riscv/thead.md (th_int_push): New pattern. (th_int_pop): new pattern. gcc/testsuite/ChangeLog: * gcc.target/riscv/xtheadint-push-pop.c: New test.
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Original file line number | Diff line number | Diff line change |
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/* { dg-do compile } */ | ||
/* { dg-options "-march=rv32gc_xtheadint -mabi=ilp32d" { target { rv32 } } } */ | ||
/* { dg-options "-march=rv64gc_xtheadint -mabi=lp64d" { target { rv64 } } } */ | ||
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extern void f (void); | ||
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__attribute__ ((interrupt)) | ||
void func_default (void) | ||
{ | ||
f (); | ||
} | ||
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__attribute__ ((interrupt ("machine"))) | ||
void func_machine (void) | ||
{ | ||
f (); | ||
} | ||
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/* { dg-final { scan-assembler-times {\mth\.ipush\M} 2 { target { rv32 } } } } */ | ||
/* { dg-final { scan-assembler-times {\mth\.ipop\M} 2 { target { rv32 } } } } */ | ||
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__attribute__ ((interrupt ("user"))) | ||
void func_usr (void) | ||
{ | ||
f (); | ||
} | ||
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__attribute__ ((interrupt ("supervisor"))) | ||
void func_supervisor (void) | ||
{ | ||
f (); | ||
} | ||
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/* { dg-final { scan-assembler-not {\mth\.ipush\M} { target { rv64 } } } } */ | ||
/* { dg-final { scan-assembler-not {\mth\.ipop\M} { target { rv64 } } } } */ |