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Two issues have been observed in current riscv_expand_conditional_move implementation. 1. Before introduction of TARGET_XTHEADCONDMOV, op0 of comparision expression is used for mode comparision with word_mode, but after TARGET_XTHEADCONDMOV megered with TARGET_SFB_ALU, dest of if-then-else is used for mode comparision with word_mode, and from md file mode of dest is DI or SI which can be different with word_mode in RV64. 2. TARGET_XTHEADCONDMOV cannot be generated when the mode of the comparison is E_VOID. This patch solves the issues above. Provide an example from the newly added test case. Testcase: int ConNmv_reg_reg_reg(int x, int y, int z, int n){ if (x != y) return z; return n; } Cflags: -O2 -march=rv64gc_xtheadcondmov -mabi=lp64d before patch: ConNmv_reg_reg_reg: bne a0,a1,.L23 mv a2,a3 .L23: mv a0,a2 ret after patch: ConNmv_reg_reg_reg: sub a1,a0,a1 th.mveqz a2,zero,a1 th.mvnez a3,zero,a1 or a0,a2,a3 ret Co-Authored by: Fei Gao <gaofei@eswincomputing.com> Signed-off-by: Die Li <lidie@eswincomputing.com> gcc/ChangeLog: * config/riscv/riscv.cc (riscv_expand_conditional_move): Fix mode checking. gcc/testsuite/ChangeLog: * gcc.target/riscv/xtheadcondmov-indirect-rv32.c: New test. * gcc.target/riscv/xtheadcondmov-indirect-rv64.c: New test.
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May 20, 2023
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gcc/testsuite/gcc.target/riscv/xtheadcondmov-indirect-rv32.c
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/* { dg-do compile } */ | ||
/* { dg-options "-O2 -march=rv32gc_xtheadcondmov -mabi=ilp32 -mriscv-attribute" } */ | ||
/* { dg-skip-if "" { *-*-* } { "-O0" "-Os" "-Og" } } */ | ||
/* { dg-final { check-function-bodies "**" "" } } */ | ||
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/* | ||
**ConEmv_imm_imm_reg: | ||
** addi a5,a0,-1000 | ||
** li a0,10 | ||
** th.mvnez a0,zero,a5 | ||
** th.mveqz a1,zero,a5 | ||
** or a0,a0,a1 | ||
** ret | ||
*/ | ||
int ConEmv_imm_imm_reg(int x, int y){ | ||
if (x == 1000) return 10; | ||
return y; | ||
} | ||
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/* | ||
**ConEmv_imm_reg_reg: | ||
** addi a5,a0,-1000 | ||
** th.mvnez a1,zero,a5 | ||
** th.mveqz a2,zero,a5 | ||
** or a0,a1,a2 | ||
** ret | ||
*/ | ||
int ConEmv_imm_reg_reg(int x, int y, int z){ | ||
if (x == 1000) return y; | ||
return z; | ||
} | ||
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/* | ||
**ConEmv_reg_imm_reg: | ||
** sub a1,a0,a1 | ||
** li a0,10 | ||
** th.mvnez a0,zero,a1 | ||
** th.mveqz a2,zero,a1 | ||
** or a0,a0,a2 | ||
** ret | ||
*/ | ||
int ConEmv_reg_imm_reg(int x, int y, int z){ | ||
if (x == y) return 10; | ||
return z; | ||
} | ||
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/* | ||
**ConEmv_reg_reg_reg: | ||
** sub a1,a0,a1 | ||
** th.mvnez a2,zero,a1 | ||
** th.mveqz a3,zero,a1 | ||
** or a0,a2,a3 | ||
** ret | ||
*/ | ||
int ConEmv_reg_reg_reg(int x, int y, int z, int n){ | ||
if (x == y) return z; | ||
return n; | ||
} | ||
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/* | ||
**ConNmv_imm_imm_reg: | ||
** li a5,9998336 | ||
** addi a4,a0,-1000 | ||
** addi a5,a5,1664 | ||
** th.mvnez a1,zero,a4 | ||
** th.mveqz a5,zero,a4 | ||
** or a0,a1,a5 | ||
** ret | ||
*/ | ||
int ConNmv_imm_imm_reg(int x, int y){ | ||
if (x != 1000) return 10000000; | ||
return y; | ||
} | ||
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/* | ||
**ConNmv_imm_reg_reg: | ||
** addi a5,a0,-1000 | ||
** th.mveqz a1,zero,a5 | ||
** th.mvnez a2,zero,a5 | ||
** or a0,a1,a2 | ||
** ret | ||
*/ | ||
int ConNmv_imm_reg_reg(int x, int y, int z){ | ||
if (x != 1000) return y; | ||
return z; | ||
} | ||
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/* | ||
**ConNmv_reg_imm_reg: | ||
** sub a1,a0,a1 | ||
** li a0,10 | ||
** th.mveqz a0,zero,a1 | ||
** th.mvnez a2,zero,a1 | ||
** or a0,a0,a2 | ||
** ret | ||
*/ | ||
int ConNmv_reg_imm_reg(int x, int y, int z){ | ||
if (x != y) return 10; | ||
return z; | ||
} | ||
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/* | ||
**ConNmv_reg_reg_reg: | ||
** sub a1,a0,a1 | ||
** th.mveqz a2,zero,a1 | ||
** th.mvnez a3,zero,a1 | ||
** or a0,a2,a3 | ||
** ret | ||
*/ | ||
int ConNmv_reg_reg_reg(int x, int y, int z, int n){ | ||
if (x != y) return z; | ||
return n; | ||
} | ||
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/* { dg-final { scan-assembler ".attribute arch, \"rv32i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_xtheadcondmov1p0\"" } } */ |
116 changes: 116 additions & 0 deletions
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gcc/testsuite/gcc.target/riscv/xtheadcondmov-indirect-rv64.c
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/* { dg-do compile } */ | ||
/* { dg-options "-O2 -march=rv64gc_xtheadcondmov -mabi=lp64d -mriscv-attribute" } */ | ||
/* { dg-skip-if "" { *-*-* } { "-O0" "-Os" "-Og" } } */ | ||
/* { dg-final { check-function-bodies "**" "" } } */ | ||
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/* | ||
**ConEmv_imm_imm_reg: | ||
** addi a5,a0,-1000 | ||
** li a0,10 | ||
** th.mvnez a0,zero,a5 | ||
** th.mveqz a1,zero,a5 | ||
** or a0,a0,a1 | ||
** ret | ||
*/ | ||
int ConEmv_imm_imm_reg(int x, int y){ | ||
if (x == 1000) return 10; | ||
return y; | ||
} | ||
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/* | ||
**ConEmv_imm_reg_reg: | ||
** addi a5,a0,-1000 | ||
** th.mvnez a1,zero,a5 | ||
** th.mveqz a2,zero,a5 | ||
** or a0,a1,a2 | ||
** ret | ||
*/ | ||
int ConEmv_imm_reg_reg(int x, int y, int z){ | ||
if (x == 1000) return y; | ||
return z; | ||
} | ||
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/* | ||
**ConEmv_reg_imm_reg: | ||
** sub a1,a0,a1 | ||
** li a0,10 | ||
** th.mvnez a0,zero,a1 | ||
** th.mveqz a2,zero,a1 | ||
** or a0,a0,a2 | ||
** ret | ||
*/ | ||
int ConEmv_reg_imm_reg(int x, int y, int z){ | ||
if (x == y) return 10; | ||
return z; | ||
} | ||
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/* | ||
**ConEmv_reg_reg_reg: | ||
** sub a1,a0,a1 | ||
** th.mvnez a2,zero,a1 | ||
** th.mveqz a3,zero,a1 | ||
** or a0,a2,a3 | ||
** ret | ||
*/ | ||
int ConEmv_reg_reg_reg(int x, int y, int z, int n){ | ||
if (x == y) return z; | ||
return n; | ||
} | ||
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/* | ||
**ConNmv_imm_imm_reg: | ||
** li a5,9998336 | ||
** addi a4,a0,-1000 | ||
** addi a5,a5,1664 | ||
** th.mvnez a1,zero,a4 | ||
** th.mveqz a5,zero,a4 | ||
** or a0,a1,a5 | ||
** ret | ||
*/ | ||
int ConNmv_imm_imm_reg(int x, int y){ | ||
if (x != 1000) return 10000000; | ||
return y; | ||
} | ||
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/* | ||
**ConNmv_imm_reg_reg: | ||
** addi a5,a0,-1000 | ||
** th.mveqz a1,zero,a5 | ||
** th.mvnez a2,zero,a5 | ||
** or a0,a1,a2 | ||
** ret | ||
*/ | ||
int ConNmv_imm_reg_reg(int x, int y, int z){ | ||
if (x != 1000) return y; | ||
return z; | ||
} | ||
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/* | ||
**ConNmv_reg_imm_reg: | ||
** sub a1,a0,a1 | ||
** li a0,10 | ||
** th.mveqz a0,zero,a1 | ||
** th.mvnez a2,zero,a1 | ||
** or a0,a0,a2 | ||
** ret | ||
*/ | ||
int ConNmv_reg_imm_reg(int x, int y, int z){ | ||
if (x != y) return 10; | ||
return z; | ||
} | ||
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/* | ||
**ConNmv_reg_reg_reg: | ||
** sub a1,a0,a1 | ||
** th.mveqz a2,zero,a1 | ||
** th.mvnez a3,zero,a1 | ||
** or a0,a2,a3 | ||
** ret | ||
*/ | ||
int ConNmv_reg_reg_reg(int x, int y, int z, int n){ | ||
if (x != y) return z; | ||
return n; | ||
} | ||
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/* { dg-final { scan-assembler ".attribute arch, \"rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_xtheadcondmov1p0\"" } } */ |