Revert "RISC-V: Support highpart overlap for vext.vf"

This reverts commit 6268589.
gcc-mirror · Apr 24, 2024 · 8bcefc2 · 8bcefc2
1 parent 3091f1d
commit 8bcefc2
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Showing 5 changed files with 10 additions and 234 deletions.
diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
@@ -3730,24 +3730,23 @@
 
 ;; Vector Double-Widening Sign-extend and Zero-extend.
 (define_insn "@pred_<optab><mode>_vf2"
-  [(set (match_operand:VWEXTI 0 "register_operand"                 "=vr,   vr,   vr,   vr,  vr,    vr, ?&vr, ?&vr")
+  [(set (match_operand:VWEXTI 0 "register_operand"            "=&vr,&vr")
 	(if_then_else:VWEXTI
 	  (unspec:<VM>
-	    [(match_operand:<VM> 1 "vector_mask_operand"         "vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1")
-	     (match_operand 4 "vector_length_operand"            "   rK,   rK,   rK,   rK,   rK,   rK,   rK,   rK")
-	     (match_operand 5 "const_int_operand"                "    i,    i,    i,    i,    i,    i,    i,    i")
-	     (match_operand 6 "const_int_operand"                "    i,    i,    i,    i,    i,    i,    i,    i")
-	     (match_operand 7 "const_int_operand"                "    i,    i,    i,    i,    i,    i,    i,    i")
+	    [(match_operand:<VM> 1 "vector_mask_operand"         "vmWc1,vmWc1")
+	     (match_operand 4 "vector_length_operand"            "   rK,   rK")
+	     (match_operand 5 "const_int_operand"                "    i,    i")
+	     (match_operand 6 "const_int_operand"                "    i,    i")
+	     (match_operand 7 "const_int_operand"                "    i,    i")
 	     (reg:SI VL_REGNUM)
 	     (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
 	  (any_extend:VWEXTI
-	    (match_operand:<V_DOUBLE_TRUNC> 3 "register_operand" "  W21,  W21,  W42,  W42,  W84,  W84,   vr,   vr"))
-	  (match_operand:VWEXTI 2 "vector_merge_operand"         "   vu,    0,   vu,    0,   vu,    0,   vu,    0")))]
+	    (match_operand:<V_DOUBLE_TRUNC> 3 "register_operand" "   vr,   vr"))
+	  (match_operand:VWEXTI 2 "vector_merge_operand"         "   vu,    0")))]
   "TARGET_VECTOR"
   "v<sz>ext.vf2\t%0,%3%p1"
   [(set_attr "type" "vext")
-   (set_attr "mode" "<MODE>")
-   (set_attr "vconstraint" "W21,W21,W42,W42,W84,W84,no,no")])
+   (set_attr "mode" "<MODE>")])
 
 ;; Vector Quad-Widening Sign-extend and Zero-extend.
 (define_insn "@pred_<optab><mode>_vf4"

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-4.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-4.c
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-5.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-5.c
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-6.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-6.c
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/unop_v_constraint-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/unop_v_constraint-2.c
@@ -30,7 +30,7 @@ void f1 (void * in, void *out)
 **	vle16\.v\tv[0-9]+,0\([a-x0-9]+\)
 **	vsext\.vf2\tv[0-9]+,\s*v[0-9]+
 **  ...
-**	vsext\.vf2\tv[0-9]+,\s*v[0-9]+,\s*v0.t
+**	vsext\.vf2\tv[1-9][0-9]?,\s*v[0-9]+,\s*v0.t
 **	vse64\.v\tv[0-9]+,0\([a-x0-9]+\)
 **	ret
 */