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RISC-V: Support zicsr and zifencei extension for -march.
- CSR related instructions and fence instructions has to be splitted from baseline ISA, zicsr and zifencei are corresponding sub-extension. gcc/ChangeLog: * common/config/riscv/riscv-common.c (riscv_implied_info): d and f implied zicsr. (riscv_ext_flag_table): Handle zicsr and zifencei. * config/riscv/riscv-opts.h (MASK_ZICSR): New. (MASK_ZIFENCEI): Ditto. (TARGET_ZICSR): Ditto. (TARGET_ZIFENCEI): Ditto. * config/riscv/riscv.md (clear_cache): Check TARGET_ZIFENCEI. (fence_i): Ditto. * config/riscv/riscv.opt (riscv_zi_subext): New. gcc/testsuite/ChangeLog: * gcc.target/riscv/arch-8.c: New. * gcc.target/riscv/attribute-14.c: Ditto.
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Original file line number | Diff line number | Diff line change |
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@@ -0,0 +1,5 @@ | ||
/* { dg-do compile } */ | ||
/* { dg-options "-O -march=rv32id_zicsr_zifence -mabi=ilp32" } */ | ||
int foo() | ||
{ | ||
} |
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Original file line number | Diff line number | Diff line change |
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@@ -0,0 +1,6 @@ | ||
/* { dg-do compile } */ | ||
/* { dg-options "-O -mriscv-attribute -march=rv32if -mabi=ilp32" } */ | ||
int foo() | ||
{ | ||
} | ||
/* { dg-final { scan-assembler ".attribute arch, \"rv32i2p0_f2p0_zicsr2p0\"" } } */ |