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Tesselated via #1391
Tesselated via #1391
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Sourcery Code Quality Report✅ Merging this PR will increase code quality in the affected files by 1.17%.
Here are some functions in these files that still need a tune-up:
Legend and ExplanationThe emojis denote the absolute quality of the code:
The 👍 and 👎 indicate whether the quality has improved or gotten worse with this pull request. Please see our documentation here for details on how these metrics are calculated. We are actively working on this report - lots more documentation and extra metrics to come! Help us improve this quality report! |
Codecov Report
@@ Coverage Diff @@
## main #1391 +/- ##
==========================================
+ Coverage 69.49% 69.57% +0.07%
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Files 366 366
Lines 21913 21972 +59
Branches 3141 3147 +6
==========================================
+ Hits 15229 15286 +57
- Misses 5781 5782 +1
- Partials 903 904 +1
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Looks great! What is And I'm wondering, could we somehow move the min and max size in the via definition in the PDKs? |
layer_port is an argument in the original via_stack function, I think it sets the layer on which the electrical port is We could do something like this: (1) New defaults to None
(2) Default to some PDK value if None:
I don't know if we have such defaults yet, or what the best way to define /access them would be |
Looks great, thank you Simon, yes, moving technology specific values to the PDK can be done easily on each PDK, or we can start using |
via_stack_from_rules is like via_stack, but instead of using hardcoded via sizes, it calculates how big the vias have to be (above a minimum size) given spacing and inclusion rules to maximize number of vias and via area
Only useful if your foundry allows you to change these things of course
Could be more general for other via stack functions
@HelgeGehring
For instance, here VIA1 and VIA2 have the same sizing and spacing rules, but different inclusions, and VIA2 ends up being sized larger: