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decoder.isa
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decoder.isa
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// -*- mode:c++ -*-
// Copyright (c) 2015 RISC-V Foundation
// Copyright (c) 2017 The University of Virginia
// Copyright (c) 2020 Barkhausen Institut
// Copyright (c) 2021 StreamComputing Corp
// Copyright (c) 2022 Google LLC
// Copyright (c) 2024 University of Rostock
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met: redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer;
// redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution;
// neither the name of the copyright holders nor the names of its
// contributors may be used to endorse or promote products derived from
// this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
////////////////////////////////////////////////////////////////////
//
// The RISC-V ISA decoder
//
// In theory, all registers should be sign extended if not operating in the
// full MXLEN register, but that will cause memory address out of range as it is
// always regarded as uint64. So we'll zero extend PC related registers and
// memory address, and sign extend others.
decode QUADRANT default Unknown::unknown() {
0x0: decode COPCODE {
0x0: CIAddi4spnOp::c_addi4spn({{
imm = CIMM8<1:1> << 2 |
CIMM8<0:0> << 3 |
CIMM8<7:6> << 4 |
CIMM8<5:2> << 6;
}}, {{
if (imm == 0)
return std::make_shared<IllegalInstFault>("immediate = 0",
machInst);
Rp2 = rvSext(sp + imm);
}}, uint64_t);
format CompressedLoad {
0x1: c_fld({{
offset = CIMM3 << 3 | CIMM2 << 6;
}}, {{
STATUS status = xc->readMiscReg(MISCREG_STATUS);
if (status.fs == FPUStatus::OFF)
return std::make_shared<IllegalInstFault>("FPU is off",
machInst);
// Mutating any floating point register changes the FS bit
// of the STATUS CSR.
status.fs = FPUStatus::DIRTY;
xc->setMiscReg(MISCREG_STATUS, status);
Fp2_bits = Mem;
}}, {{
EA = rvZext(Rp1 + offset);
}});
0x2: c_lw({{
offset = CIMM2<1:1> << 2 |
CIMM3 << 3 |
CIMM2<0:0> << 6;
}}, {{
Rp2_sd = Mem_sw;
}}, {{
EA = rvZext(Rp1 + offset);
}});
0x3: decode RVTYPE {
0x0: c_flw({{
offset = CIMM2<1:1> << 2 |
CIMM3 << 3 |
CIMM2<0:0> << 6;
}}, {{
STATUS status = xc->readMiscReg(MISCREG_STATUS);
if (status.fs == FPUStatus::OFF)
return std::make_shared<IllegalInstFault>("FPU is off",
machInst);
status.fs = FPUStatus::DIRTY;
xc->setMiscReg(MISCREG_STATUS, status);
freg_t fd = freg(f32(Mem_uw));
Fp2_bits = fd.v;
}}, {{
EA = (uint32_t)(Rp1_uw + offset);
}});
0x1: c_ld({{
offset = CIMM3 << 3 | CIMM2 << 6;
}}, {{
Rp2_sd = Mem_sd;
}}, {{
EA = Rp1 + offset;
}});
}
}
0x4: decode CFUNCT6LOW3 {
format CompressedLoad {
0x0: c_lbu({{
offset = (CIMM2<0:0> << 1) | CIMM2<1:1>;
}}, {{
Rp2 = Mem_ub;
}}, {{
EA = rvZext(Rp1 + offset);
}});
0x1: decode CFUNCT1BIT6 {
0x0: c_lhu({{
offset = CIMM2<0:0> << 1;
}}, {{
Rp2 = Mem_uh;
}}, {{
EA = rvZext(Rp1 + offset);
}});
0x1: c_lh({{
offset = CIMM2<0:0> << 1;
}}, {{
Rp2_sd = Mem_sh;
}}, {{
EA = rvZext(Rp1 + offset);
}});
}
}
format CompressedStore {
0x2: c_sb({{
offset = (CIMM2<0:0> << 1) | CIMM2<1:1>;
}}, {{
Mem_ub = Rp2_ub;
}}, ea_code={{
EA = rvZext(Rp1 + offset);
}});
0x3: c_sh({{
offset = (CIMM2<0:0> << 1);
}}, {{
Mem_uh = Rp2_uh;
}}, ea_code={{
EA = rvZext(Rp1 + offset);
}});
}
}
format CompressedStore {
0x5: c_fsd({{
offset = CIMM3 << 3 | CIMM2 << 6;
}}, {{
STATUS status = xc->readMiscReg(MISCREG_STATUS);
if (status.fs == FPUStatus::OFF)
return std::make_shared<IllegalInstFault>("FPU is off",
machInst);
Mem = Fp2_bits;
}}, {{
EA = rvZext(Rp1 + offset);
}});
0x6: c_sw({{
offset = CIMM2<1:1> << 2 |
CIMM3 << 3 |
CIMM2<0:0> << 6;
}}, {{
Mem_uw = Rp2_uw;
}}, ea_code={{
EA = rvZext(Rp1 + offset);
}});
0x7: decode RVTYPE {
0x0: c_fsw({{
offset = CIMM2<1:1> << 2 |
CIMM3 << 3 |
CIMM2<0:0> << 6;
}}, {{
STATUS status = xc->readMiscReg(MISCREG_STATUS);
if (status.fs == FPUStatus::OFF)
return std::make_shared<IllegalInstFault>("FPU is off",
machInst);
Mem_uw = unboxF32(boxF32(Fp2_bits));
}}, {{
EA = (uint32_t)(Rp1_uw + offset);
}});
0x1: c_sd({{
offset = CIMM3 << 3 | CIMM2 << 6;
}}, {{
Mem_ud = Rp2_ud;
}}, {{
EA = Rp1 + offset;
}});
}
}
}
0x1: decode COPCODE {
0x0: CIOp::c_addi({{
imm = sext<6>(CIMM5 | (CIMM1 << 5));
}}, {{
if ((RC1 == 0) != (imm == 0)) {
if (RC1 == 0) {
// imm != 0 is HINT
} else {
// imm == 0 is HINT
}
}
Rc1_sd = rvSext(Rc1_sd + imm);
}});
0x1: decode RVTYPE {
0x0: CJOp::c_jal({{
ra_sw = NPC_uw;
NPC_uw = PC_uw + imm;
}}, IsDirectControl, IsUncondControl, IsCall);
0x1: CIOp::c_addiw({{
imm = sext<6>(CIMM5 | (CIMM1 << 5));
}}, {{
if (RC1 == 0) {
return std::make_shared<IllegalInstFault>(
"source reg x0", machInst);
}
Rc1_sw = (int32_t)(Rc1_sw + imm);
}});
}
0x2: CIOp::c_li({{
imm = sext<6>(CIMM5 | (CIMM1 << 5));
}}, {{
// RC1 == 0 is HINT
Rc1_sd = imm;
}});
0x3: decode RC1 {
0x2: CIOp::c_addi16sp({{
imm = sext<10>((CIMM5<4:4> << 4) |
(CIMM5<0:0> << 5) |
(CIMM5<3:3> << 6) |
(CIMM5<2:1> << 7) |
(CIMM1 << 9));
}}, {{
if (imm == 0) {
return std::make_shared<IllegalInstFault>(
"immediate = 0", machInst);
}
sp_sd = rvSext(sp_sd + imm);
}});
default: CIOp::c_lui({{
imm = sext<6>(CIMM5 | (CIMM1 << 5)) << 12;
}}, {{
// RC1 == 0 is HINT
if (imm == 0) {
return std::make_shared<IllegalInstFault>(
"immediate = 0", machInst);
}
Rc1_sd = imm;
}});
}
0x4: decode CFUNCT2HIGH {
format CIOp {
0x0: c_srli({{
imm = CIMM5 | (CIMM1 << 5);
}}, {{
if (rvSelect((bool)CIMM1, false)) {
return std::make_shared<IllegalInstFault>(
"shmat[5] != 0", machInst);
}
if (imm == 0) {
// C.SRLI64, HINT for RV32/RV64
}
// The MSB can never be 1, hence no need to sign ext.
Rp1 = rvZext(Rp1) >> imm;
}}, uint64_t);
0x1: c_srai({{
imm = CIMM5 | (CIMM1 << 5);
}}, {{
if (rvSelect((bool)CIMM1, false)) {
return std::make_shared<IllegalInstFault>(
"shmat[5] != 0", machInst);
}
if (imm == 0) {
// C.SRAI64, HINT for RV32/RV64
}
Rp1_sd = rvSext(Rp1_sd) >> imm;
}}, uint64_t);
0x2: c_andi({{
imm = CIMM5;
if (CIMM1 > 0)
imm |= ~((uint64_t)0x1F);
}}, {{
Rp1 = rvSext(Rp1 & imm);
}}, uint64_t);
}
format CompressedROp {
0x3: decode CFUNCT1 {
0x0: decode CFUNCT2LOW {
0x0: c_sub({{
Rp1 = rvSext(Rp1 - Rp2);
}});
0x1: c_xor({{
Rp1 = rvSext(Rp1 ^ Rp2);
}});
0x2: c_or({{
Rp1 = rvSext(Rp1 | Rp2);
}});
0x3: c_and({{
Rp1 = rvSext(Rp1 & Rp2);
}});
}
0x1: decode CFUNCT2LOW {
0x0: decode RVTYPE {
0x1: c_subw({{
Rp1_sd = (int32_t)Rp1_sd - Rp2_sw;
}});
}
0x1: decode RVTYPE {
0x1: c_addw({{
Rp1_sd = (int32_t)Rp1_sd + Rp2_sw;
}});
}
0x2: c_mul({{
Rp1_sd = rvSext(Rp1_sd * Rp2_sd);
}}, IntMultOp);
0x3: decode RP2 {
0x0: c_zext_b({{
Rp1 = Rp1 & 0xFFULL;
}});
0x1: c_sext_b({{
Rp1 = sext<8>(Rp1 & 0xFFULL);
}});
0x2: c_zext_h({{
Rp1 = Rp1 & 0xFFFFULL;
}});
0x3: c_sext_h({{
Rp1 = sext<16>(Rp1 & 0xFFFFULL);
}});
0x4: decode RVTYPE {
0x1: c_zext_w({{
Rp1 = bits(Rp1, 31, 0);
}});
}
0x5: c_not({{
Rp1 = ~Rp1;
}});
}
}
}
}
}
0x5: CJOp::c_j({{
NPC = rvZext(PC + imm);
}}, IsDirectControl, IsUncondControl);
format CBOp {
0x6: c_beqz({{
if (rvSext(Rp1) == 0)
NPC = rvZext(PC + imm);
else
NPC = NPC;
}}, IsDirectControl, IsCondControl);
0x7: c_bnez({{
if (rvSext(Rp1) != 0)
NPC = rvZext(PC + imm);
else
NPC = NPC;
}}, IsDirectControl, IsCondControl);
}
}
0x2: decode COPCODE {
0x0: CIOp::c_slli({{
imm = CIMM5 | (CIMM1 << 5);
}}, {{
if (rvSelect((bool)CIMM1, false)) {
return std::make_shared<IllegalInstFault>(
"shmat[5] != 0", machInst);
}
if (imm == 0) {
// C.SLLI64, HINT for RV32/RV64
}
// RC1 == 0 is HINT
Rc1 = rvSext(Rc1 << imm);
}}, uint64_t);
format CompressedLoad {
0x1: c_fldsp({{
offset = CIMM5<4:3> << 3 |
CIMM1 << 5 |
CIMM5<2:0> << 6;
}}, {{
STATUS status = xc->readMiscReg(MISCREG_STATUS);
if (status.fs == FPUStatus::OFF)
return std::make_shared<IllegalInstFault>("FPU is off",
machInst);
status.fs = FPUStatus::DIRTY;
xc->setMiscReg(MISCREG_STATUS, status);
Fc1_bits = Mem;
}}, {{
EA = rvZext(sp + offset);
}});
0x2: c_lwsp({{
offset = CIMM5<4:2> << 2 |
CIMM1 << 5 |
CIMM5<1:0> << 6;
}}, {{
if (RC1 == 0) {
return std::make_shared<IllegalInstFault>(
"source reg x0", machInst);
}
Rc1_sw = Mem_sw;
}}, {{
EA = rvZext(sp + offset);
}});
0x3: decode RVTYPE {
0x0: c_flwsp({{
offset = CIMM5<4:2> << 2 |
CIMM1 << 5 |
CIMM5<1:0> << 6;
}}, {{
STATUS status = xc->readMiscReg(MISCREG_STATUS);
if (status.fs == FPUStatus::OFF)
return std::make_shared<IllegalInstFault>("FPU is off",
machInst);
status.fs = FPUStatus::DIRTY;
xc->setMiscReg(MISCREG_STATUS, status);
freg_t fd;
fd = freg(f32(Mem_uw));
Fc1_bits = fd.v;
}}, {{
EA = (uint32_t)(sp_uw + offset);
}});
0x1: c_ldsp({{
offset = CIMM5<4:3> << 3 |
CIMM1 << 5 |
CIMM5<2:0> << 6;
}}, {{
if (RC1 == 0) {
return std::make_shared<IllegalInstFault>(
"source reg x0", machInst);
}
Rc1_sd = Mem_sd;
}}, {{
EA = sp + offset;
}});
}
}
0x4: decode CFUNCT1 {
0x0: decode RC2 {
0x0: CJump::c_jr({{
if (RC1 == 0) {
return std::make_shared<IllegalInstFault>(
"source reg x0", machInst);
}
NPC = rvZext(Rc1 & (~0x1));
}}, IsIndirectControl, IsUncondControl);
default: CROp::c_mv({{
// RC1 == 0 is HINT
Rc1 = rvSext(Rc2);
}});
}
0x1: decode RC2 {
0x0: decode RC1 {
0x0: SystemOp::c_ebreak({{
// NB: Semihosting spec requires uncompressed ebreak,
// so this instruction does not check for semihosting.
return std::make_shared<BreakpointFault>(
xc->pcState());
}}, IsSerializeAfter, IsNonSpeculative, No_OpClass);
default: CJump::c_jalr({{
ra = rvSext(NPC);
NPC = rvZext(Rc1 & (~0x1));
}}, IsIndirectControl, IsUncondControl, IsCall);
}
default: CompressedROp::c_add({{
// RC1 == 0 is HINT
Rc1_sd = rvSext(Rc1_sd + Rc2_sd);
}});
}
}
format CompressedStore {
0x5: c_fsdsp({{
offset = CIMM6<5:3> << 3 |
CIMM6<2:0> << 6;
}}, {{
STATUS status = xc->readMiscReg(MISCREG_STATUS);
if (status.fs == FPUStatus::OFF)
return std::make_shared<IllegalInstFault>("FPU is off",
machInst);
Mem_ud = Fc2_bits;
}}, {{
EA = rvZext(sp + offset);
}});
0x6: c_swsp({{
offset = CIMM6<5:2> << 2 |
CIMM6<1:0> << 6;
}}, {{
Mem_uw = Rc2_uw;
}}, {{
EA = rvZext(sp + offset);
}});
0x7: decode RVTYPE {
0x0: c_fswsp({{
offset = CIMM6<5:2> << 2 |
CIMM6<1:0> << 6;
}}, {{
STATUS status = xc->readMiscReg(MISCREG_STATUS);
if (status.fs == FPUStatus::OFF)
return std::make_shared<IllegalInstFault>("FPU is off",
machInst);
Mem_uw = unboxF32(boxF32(Fc2_bits));
}}, {{
EA = (uint32_t)(sp_uw + offset);
}});
0x1: c_sdsp({{
offset = CIMM6<5:3> << 3 |
CIMM6<2:0> << 6;
}}, {{
Mem = Rc2;
}}, {{
EA = sp + offset;
}});
}
}
}
0x3: decode OPCODE5 {
0x00: decode FUNCT3 {
format Load {
0x0: lb({{
Rd_sd = Mem_sb;
}});
0x1: lh({{
Rd_sd = Mem_sh;
}});
0x2: lw({{
Rd_sd = Mem_sw;
}});
0x3: decode RVTYPE {
0x1: ld({{
Rd_sd = Mem_sd;
}});
}
0x4: lbu({{
Rd = Mem_ub;
}});
0x5: lhu({{
Rd = Mem_uh;
}});
0x6: decode RVTYPE {
0x1: lwu({{
Rd = Mem_uw;
}});
}
}
}
0x01: decode FUNCT3 {
format Load {
0x1: flh({{
STATUS status = xc->readMiscReg(MISCREG_STATUS);
if (status.fs == FPUStatus::OFF)
return std::make_shared<IllegalInstFault>(
"FPU is off", machInst);
status.fs = FPUStatus::DIRTY;
xc->setMiscReg(MISCREG_STATUS, status);
freg_t fd;
fd = freg(f16(Mem_uh));
Fd_bits = fd.v;
}}, inst_flags=FloatMemReadOp);
0x2: flw({{
STATUS status = xc->readMiscReg(MISCREG_STATUS);
if (status.fs == FPUStatus::OFF)
return std::make_shared<IllegalInstFault>(
"FPU is off", machInst);
status.fs = FPUStatus::DIRTY;
xc->setMiscReg(MISCREG_STATUS, status);
freg_t fd;
fd = freg(f32(Mem_uw));
Fd_bits = fd.v;
}}, inst_flags=FloatMemReadOp);
0x3: fld({{
STATUS status = xc->readMiscReg(MISCREG_STATUS);
if (status.fs == FPUStatus::OFF)
return std::make_shared<IllegalInstFault>(
"FPU is off", machInst);
status.fs = FPUStatus::DIRTY;
xc->setMiscReg(MISCREG_STATUS, status);
freg_t fd;
fd = freg(f64(Mem));
Fd_bits = fd.v;
}}, inst_flags=FloatMemReadOp);
}
0x0: decode MOP {
0x0: decode LUMOP {
0x00: decode NF {
0x00: VleOp::vle8_v({{
if ((machInst.vm || elem_mask(v0, ei)) &&
i < this->microVl) {
Vd_ub[i] = Mem_vc.as<uint8_t>()[i];
} else {
Vd_ub[i] = Vs2_ub[i];
}
}}, inst_flags=SimdUnitStrideLoadOp);
format VlSegOp {
0x01: vlseg2e8_v({{
if ((machInst.vm || elem_mask_vseg(v0, ei + (field * micro_elems), 2)) &&
i < this->microVl) {
Vd_ub[i] = Mem_vc.as<uint8_t>()[i];
} else {
Vd_ub[i] = Vs2_ub[i];
}
}}, inst_flags=SimdUnitStrideSegmentedLoadOp);
0x02: vlseg3e8_v({{
if ((machInst.vm || elem_mask_vseg(v0, ei + (field * micro_elems), 3)) &&
i < this->microVl) {
Vd_ub[i] = Mem_vc.as<uint8_t>()[i];
} else {
Vd_ub[i] = Vs2_ub[i];
}
}}, inst_flags=SimdUnitStrideSegmentedLoadOp);
0x03: vlseg4e8_v({{
if ((machInst.vm || elem_mask_vseg(v0, ei + (field * micro_elems), 4)) &&
i < this->microVl) {
Vd_ub[i] = Mem_vc.as<uint8_t>()[i];
} else {
Vd_ub[i] = Vs2_ub[i];
}
}}, inst_flags=SimdUnitStrideSegmentedLoadOp);
0x04: vlseg5e8_v({{
if ((machInst.vm || elem_mask_vseg(v0, ei + (field * micro_elems), 5)) &&
i < this->microVl) {
Vd_ub[i] = Mem_vc.as<uint8_t>()[i];
} else {
Vd_ub[i] = Vs2_ub[i];
}
}}, inst_flags=SimdUnitStrideSegmentedLoadOp);
0x05: vlseg6e8_v({{
if ((machInst.vm || elem_mask_vseg(v0, ei + (field * micro_elems), 6)) &&
i < this->microVl) {
Vd_ub[i] = Mem_vc.as<uint8_t>()[i];
} else {
Vd_ub[i] = Vs2_ub[i];
}
}}, inst_flags=SimdUnitStrideSegmentedLoadOp);
0x06: vlseg7e8_v({{
if ((machInst.vm || elem_mask_vseg(v0, ei + (field * micro_elems), 7)) &&
i < this->microVl) {
Vd_ub[i] = Mem_vc.as<uint8_t>()[i];
} else {
Vd_ub[i] = Vs2_ub[i];
}
}}, inst_flags=SimdUnitStrideSegmentedLoadOp);
0x07: vlseg8e8_v({{
if ((machInst.vm || elem_mask_vseg(v0, ei + (field * micro_elems), 8)) &&
i < this->microVl) {
Vd_ub[i] = Mem_vc.as<uint8_t>()[i];
} else {
Vd_ub[i] = Vs2_ub[i];
}
}}, inst_flags=SimdUnitStrideSegmentedLoadOp);
}
}
0x08: decode NF {
format VlWholeOp {
0x0: vl1re8_v({{
Vd_ub[i] = Mem_vc.as<uint8_t>()[i];
}}, inst_flags=SimdWholeRegisterLoadOp);
0x1: vl2re8_v({{
Vd_ub[i] = Mem_vc.as<uint8_t>()[i];
}}, inst_flags=SimdWholeRegisterLoadOp);
0x3: vl4re8_v({{
Vd_ub[i] = Mem_vc.as<uint8_t>()[i];
}}, inst_flags=SimdWholeRegisterLoadOp);
0x7: vl8re8_v({{
Vd_ub[i] = Mem_vc.as<uint8_t>()[i];
}}, inst_flags=SimdWholeRegisterLoadOp);
}
}
0x0b: VlmOp::vlm_v({{
Vd_ub[i] = Mem_vc.as<uint8_t>()[i];
}}, inst_flags=SimdUnitStrideMaskLoadOp);
0x10: VleOp::vle8ff_v({{
if ((machInst.vm || elem_mask(v0, ei)) &&
i < this->microVl && i < this->faultIdx) {
Vd_ub[i] = Mem_vc.as<uint8_t>()[i];
} else {
Vd_ub[i] = Vs2_ub[i];
}
}}, inst_flags=SimdUnitStrideFaultOnlyFirstLoadOp);
}
0x1: VlIndexOp::vluxei8_v({{
Vd_vu[vdElemIdx] = Mem_vc.as<vu>()[0];
}}, {{
EA = Rs1 + Vs2_ub[vs2ElemIdx];
}}, inst_flags=SimdIndexedLoadOp);
0x2: VlStrideOp::vlse8_v({{
Vd_ub[microIdx] = Mem_vc.as<uint8_t>()[0];
}}, inst_flags=SimdStridedLoadOp);
0x3: VlIndexOp::vloxei8_v({{
Vd_vu[vdElemIdx] = Mem_vc.as<vu>()[0];
}}, {{
EA = Rs1 + Vs2_ub[vs2ElemIdx];
}}, inst_flags=SimdIndexedLoadOp);
}
0x5: decode MOP {
0x0: decode LUMOP {
0x00: decode NF {
0x00: VleOp::vle16_v({{
if ((machInst.vm || elem_mask(v0, ei)) &&
i < this->microVl) {
Vd_uh[i] = Mem_vc.as<uint16_t>()[i];
} else {
Vd_uh[i] = Vs2_uh[i];
}
}}, inst_flags=SimdUnitStrideLoadOp);
format VlSegOp {
0x01: vlseg2e16_v({{
if ((machInst.vm || elem_mask_vseg(v0, ei + (field * micro_elems), 2)) &&
i < this->microVl) {
Vd_uh[i] = Mem_vc.as<uint16_t>()[i];
} else {
Vd_uh[i] = Vs2_uh[i];
}
}}, inst_flags=SimdUnitStrideSegmentedLoadOp);
0x02: vlseg3e16_v({{
if ((machInst.vm || elem_mask_vseg(v0, ei + (field * micro_elems), 3)) &&
i < this->microVl) {
Vd_uh[i] = Mem_vc.as<uint16_t>()[i];
} else {
Vd_uh[i] = Vs2_uh[i];
}
}}, inst_flags=SimdUnitStrideSegmentedLoadOp);
0x03: vlseg4e16_v({{
if ((machInst.vm || elem_mask_vseg(v0, ei + (field * micro_elems), 4)) &&
i < this->microVl) {
Vd_uh[i] = Mem_vc.as<uint16_t>()[i];
} else {
Vd_uh[i] = Vs2_uh[i];
}
}}, inst_flags=SimdUnitStrideSegmentedLoadOp);
0x04: vlseg5e16_v({{
if ((machInst.vm || elem_mask_vseg(v0, ei + (field * micro_elems), 5)) &&
i < this->microVl) {
Vd_uh[i] = Mem_vc.as<uint16_t>()[i];
} else {
Vd_uh[i] = Vs2_uh[i];
}
}}, inst_flags=SimdUnitStrideSegmentedLoadOp);
0x05: vlseg6e16_v({{
if ((machInst.vm || elem_mask_vseg(v0, ei + (field * micro_elems), 6)) &&
i < this->microVl) {
Vd_uh[i] = Mem_vc.as<uint16_t>()[i];
} else {
Vd_uh[i] = Vs2_uh[i];
}
}}, inst_flags=SimdUnitStrideSegmentedLoadOp);
0x06: vlseg7e16_v({{
if ((machInst.vm || elem_mask_vseg(v0, ei + (field * micro_elems), 7)) &&
i < this->microVl) {
Vd_uh[i] = Mem_vc.as<uint16_t>()[i];
} else {
Vd_uh[i] = Vs2_uh[i];
}
}}, inst_flags=SimdUnitStrideSegmentedLoadOp);
0x07: vlseg8e16_v({{
if ((machInst.vm || elem_mask_vseg(v0, ei + (field * micro_elems), 8)) &&
i < this->microVl) {
Vd_uh[i] = Mem_vc.as<uint16_t>()[i];
} else {
Vd_uh[i] = Vs2_uh[i];
}
}}, inst_flags=SimdUnitStrideSegmentedLoadOp);
}
}
0x08: decode NF {
format VlWholeOp {
0x0: vl1re16_v({{
Vd_uh[i] = Mem_vc.as<uint16_t>()[i];
}}, inst_flags=SimdWholeRegisterLoadOp);
0x1: vl2re16_v({{
Vd_uh[i] = Mem_vc.as<uint16_t>()[i];
}}, inst_flags=SimdWholeRegisterLoadOp);
0x3: vl4re16_v({{
Vd_uh[i] = Mem_vc.as<uint16_t>()[i];
}}, inst_flags=SimdWholeRegisterLoadOp);
0x7: vl8re16_v({{
Vd_uh[i] = Mem_vc.as<uint16_t>()[i];
}}, inst_flags=SimdWholeRegisterLoadOp);
}
}
0x10: VleOp::vle16ff_v({{
if ((machInst.vm || elem_mask(v0, ei)) &&
i < this->microVl && i < this->faultIdx) {
Vd_uh[i] = Mem_vc.as<uint16_t>()[i];
} else {
Vd_uh[i] = Vs2_uh[i];
}
}}, inst_flags=SimdUnitStrideFaultOnlyFirstLoadOp);
}
0x1: VlIndexOp::vluxei16_v({{
Vd_vu[vdElemIdx] = Mem_vc.as<vu>()[0];
}}, {{
EA = Rs1 + Vs2_uh[vs2ElemIdx];
}}, inst_flags=SimdIndexedLoadOp);
0x2: VlStrideOp::vlse16_v({{
Vd_uh[microIdx] = Mem_vc.as<uint16_t>()[0];
}}, inst_flags=SimdStridedLoadOp);
0x3: VlIndexOp::vloxei16_v({{
Vd_vu[vdElemIdx] = Mem_vc.as<vu>()[0];
}}, {{
EA = Rs1 + Vs2_uh[vs2ElemIdx];
}}, inst_flags=SimdIndexedLoadOp);
}
0x6: decode MOP {
0x0: decode LUMOP {
0x00: decode NF {
0x00: VleOp::vle32_v({{
if ((machInst.vm || elem_mask(v0, ei)) &&
i < this->microVl) {
Vd_uw[i] = Mem_vc.as<uint32_t>()[i];
} else {
Vd_uw[i] = Vs2_uw[i];
}
}}, inst_flags=SimdUnitStrideLoadOp);
format VlSegOp {
0x01: vlseg2e32_v({{
if ((machInst.vm || elem_mask_vseg(v0, ei + (field * micro_elems), 2)) &&
i < this->microVl) {
Vd_uw[i] = Mem_vc.as<uint32_t>()[i];
} else {
Vd_uw[i] = Vs2_uw[i];
}
}}, inst_flags=SimdUnitStrideSegmentedLoadOp);
0x02: vlseg3e32_v({{
if ((machInst.vm || elem_mask_vseg(v0, ei + (field * micro_elems), 3)) &&
i < this->microVl) {
Vd_uw[i] = Mem_vc.as<uint32_t>()[i];
} else {
Vd_uw[i] = Vs2_uw[i];
}
}}, inst_flags=SimdUnitStrideSegmentedLoadOp);
0x03: vlseg4e32_v({{
if ((machInst.vm || elem_mask_vseg(v0, ei + (field * micro_elems), 4)) &&
i < this->microVl) {
Vd_uw[i] = Mem_vc.as<uint32_t>()[i];
} else {
Vd_uw[i] = Vs2_uw[i];
}
}}, inst_flags=SimdUnitStrideSegmentedLoadOp);
0x04: vlseg5e32_v({{
if ((machInst.vm || elem_mask_vseg(v0, ei + (field * micro_elems), 5)) &&
i < this->microVl) {
Vd_uw[i] = Mem_vc.as<uint32_t>()[i];
} else {
Vd_uw[i] = Vs2_uw[i];
}
}}, inst_flags=SimdUnitStrideSegmentedLoadOp);
0x05: vlseg6e32_v({{
if ((machInst.vm || elem_mask_vseg(v0, ei + (field * micro_elems), 6)) &&
i < this->microVl) {
Vd_uw[i] = Mem_vc.as<uint32_t>()[i];
} else {
Vd_uw[i] = Vs2_uw[i];
}
}}, inst_flags=SimdUnitStrideSegmentedLoadOp);
0x06: vlseg7e32_v({{
if ((machInst.vm || elem_mask_vseg(v0, ei + (field * micro_elems), 7)) &&
i < this->microVl) {
Vd_uw[i] = Mem_vc.as<uint32_t>()[i];
} else {
Vd_uw[i] = Vs2_uw[i];
}
}}, inst_flags=SimdUnitStrideSegmentedLoadOp);
0x07: vlseg8e32_v({{
if ((machInst.vm || elem_mask_vseg(v0, ei + (field * micro_elems), 8)) &&
i < this->microVl) {
Vd_uw[i] = Mem_vc.as<uint32_t>()[i];
} else {
Vd_uw[i] = Vs2_uw[i];
}
}}, inst_flags=SimdUnitStrideSegmentedLoadOp);
}
}
0x08: decode NF {
format VlWholeOp {
0x0: vl1re32_v({{
Vd_uw[i] = Mem_vc.as<uint32_t>()[i];
}}, inst_flags=SimdWholeRegisterLoadOp);
0x1: vl2re32_v({{
Vd_uw[i] = Mem_vc.as<uint32_t>()[i];
}}, inst_flags=SimdWholeRegisterLoadOp);
0x3: vl4re32_v({{
Vd_uw[i] = Mem_vc.as<uint32_t>()[i];
}}, inst_flags=SimdWholeRegisterLoadOp);
0x7: vl8re32_v({{
Vd_uw[i] = Mem_vc.as<uint32_t>()[i];
}}, inst_flags=SimdWholeRegisterLoadOp);
}
}
0x10: VleOp::vle32ff_v({{
if ((machInst.vm || elem_mask(v0, ei)) &&
i < this->microVl && i < this->faultIdx) {
Vd_uw[i] = Mem_vc.as<uint32_t>()[i];
} else {
Vd_uw[i] = Vs2_uw[i];
}
}}, inst_flags=SimdUnitStrideFaultOnlyFirstLoadOp);
}
0x1: VlIndexOp::vluxei32_v({{
Vd_vu[vdElemIdx] = Mem_vc.as<vu>()[0];
}}, {{
EA = Rs1 + Vs2_uw[vs2ElemIdx];
}}, inst_flags=SimdIndexedLoadOp);
0x2: VlStrideOp::vlse32_v({{
Vd_uw[microIdx] = Mem_vc.as<uint32_t>()[0];
}}, inst_flags=SimdStridedLoadOp);
0x3: VlIndexOp::vloxei32_v({{
Vd_vu[vdElemIdx] = Mem_vc.as<vu>()[0];
}}, {{
EA = Rs1 + Vs2_uw[vs2ElemIdx];
}}, inst_flags=SimdIndexedLoadOp);
}
0x7: decode MOP {
0x0: decode LUMOP {
0x00: decode NF {
0x00: VleOp::vle64_v({{
if ((machInst.vm || elem_mask(v0, ei)) &&
i < this->microVl) {
Vd_ud[i] = Mem_vc.as<uint64_t>()[i];
} else {
Vd_ud[i] = Vs2_ud[i];
}
}}, inst_flags=SimdUnitStrideLoadOp);
format VlSegOp {
0x01: vlseg2e64_v({{
if ((machInst.vm || elem_mask_vseg(v0, ei + (field * micro_elems), 2)) &&
i < this->microVl) {
Vd_ud[i] = Mem_vc.as<uint64_t>()[i];
} else {
Vd_ud[i] = Vs2_ud[i];
}
}}, inst_flags=SimdUnitStrideSegmentedLoadOp);
0x02: vlseg3e64_v({{
if ((machInst.vm || elem_mask_vseg(v0, ei + (field * micro_elems), 3)) &&
i < this->microVl) {
Vd_ud[i] = Mem_vc.as<uint64_t>()[i];
} else {
Vd_ud[i] = Vs2_ud[i];
}
}}, inst_flags=SimdUnitStrideSegmentedLoadOp);
0x03: vlseg4e64_v({{
if ((machInst.vm || elem_mask_vseg(v0, ei + (field * micro_elems), 4)) &&
i < this->microVl) {
Vd_ud[i] = Mem_vc.as<uint64_t>()[i];
} else {
Vd_ud[i] = Vs2_ud[i];
}
}}, inst_flags=SimdUnitStrideSegmentedLoadOp);
0x04: vlseg5e64_v({{
if ((machInst.vm || elem_mask_vseg(v0, ei + (field * micro_elems), 5)) &&
i < this->microVl) {
Vd_ud[i] = Mem_vc.as<uint64_t>()[i];
} else {
Vd_ud[i] = Vs2_ud[i];
}
}}, inst_flags=SimdUnitStrideSegmentedLoadOp);
0x05: vlseg6e64_v({{
if ((machInst.vm || elem_mask_vseg(v0, ei + (field * micro_elems), 6)) &&
i < this->microVl) {
Vd_ud[i] = Mem_vc.as<uint64_t>()[i];
} else {
Vd_ud[i] = Vs2_ud[i];
}
}}, inst_flags=SimdUnitStrideSegmentedLoadOp);
0x06: vlseg7e64_v({{
if ((machInst.vm || elem_mask_vseg(v0, ei + (field * micro_elems), 7)) &&
i < this->microVl) {
Vd_ud[i] = Mem_vc.as<uint64_t>()[i];
} else {
Vd_ud[i] = Vs2_ud[i];
}
}}, inst_flags=SimdUnitStrideSegmentedLoadOp);
0x07: vlseg8e64_v({{
if ((machInst.vm || elem_mask_vseg(v0, ei + (field * micro_elems), 8)) &&
i < this->microVl) {
Vd_ud[i] = Mem_vc.as<uint64_t>()[i];
} else {
Vd_ud[i] = Vs2_ud[i];
}
}}, inst_flags=SimdUnitStrideSegmentedLoadOp);