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RVV: some rvv instructions' dest register is also considered as a src register. #1241
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Describe the bug
CPU: MinorCPU
ISA: RISCV (vector extension)
vlmul : 2
0x10200 | m5op (vnop)
0x10204 | vfmul.vv v2, v0, v0
0x10208 | vfmul.vv v2, v0, v0
0x1020c | vfmul.vv v2, v0, v0
0x10210 | vfmul.vv v2, v0, v0
0x10214 | vfmul.vv v2, v0, v0
0x10218 | vfmul.vv v2, v0, v0
0x1021c | vfmul.vv v2, v0, v0
0x10220 | vfmul.vv v2, v0, v0
0x10224 | vfmul.vv v2, v0, v0
0x10228 | vfmul.vv v2, v0, v0
0x1022c | vfmul.vv v2, v0, v0
0x10230 | vfmul.vv v2, v0, v0
0x10234 | vfmul.vv v2, v0, v0
0x10238 | vfmul.vv v2, v0, v0
0x1023c | vfmul.vv v2, v0, v0
0x10240 | m5op (vnop)
In this case, there should not be any src reg. dependencies, but there was some dependency problem on execute stage in RiscvMinorCPU.
But it acts like there are dependencies between each of the instructions.
As i debugged, the destination register 'v2' is also considered as a source register.
0x10200 | m5op (vnop)
0x10204 | vfmul.vv v2, v0, v0
0x10208 | vfmul.vv v4, v0, v0
0x1020c | vfmul.vv v6, v0, v0
0x10210 | vfmul.vv v8, v0, v0
0x10214 | vfmul.vv v10, v0, v0
0x10218 | vfmul.vv v12, v0, v0
0x1021c | vfmul.vv v14, v0, v0
0x10220 | vfmul.vv v16, v0, v0
0x10224 | vfmul.vv v18, v0, v0
0x10228 | vfmul.vv v20, v0, v0
0x1022c | vfmul.vv v22, v0, v0
0x10230 | vfmul.vv v24, v0, v0
0x10234 | vfmul.vv v26, v0, v0
0x10238 | vfmul.vv v28, v0, v0
0x1023c | vfmul.vv v30, v0, v0
0x10240 | m5op (vnop)
To make sure my opinion, i tried new assembly codes, that each vfmul.vv has different destination register.
I believe there should not be any difference on cycles between these two cases.
Affects version
23.1.0 (the latest release version)
gem5 Modifications
NOP
To Reproduce
Steps to reproduce the behavior. Please assume starting from a clean repository:
Compile gem5 with command ...
scons build/ALL/gem5.debug -j $(nrpoc)
Compile c++ code below with "riscv64-unknown-elf-g++"
`./build/ALL/gem5.debug --debug-flags=Fetch,Decode,MinorExecute script.py vfmul_vv_example_code --cpu RiscvMinorCPU
Terminal Output
With MinorExecute Debug Flags, you can find an dependency issue due to the cycles.
At Scoreboard::canInstIssue (src/cpu/minor/scoreboard.cc : 208), I could find that dest reg is also considered as a src register.
Host Operating System
Ubuntu 22.04
Host ISA
RISC-V Vector Extension
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