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hw: prepare ARMv8 EL2 mode appropriatedly to run Rockchip 3588 #4759
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Instead of re-using the register values found in HCR_EL2 and CPTR_EL2 and setting single bits within them, define the complete content to prevent inconsistent hardware/hypervisor state. Ref genodelabs#4759
@mickenx I've prepared commit 9c6b97e that shall also solve your initial bootstrap problems without replacing our crt0.so. I would be happy, if you could try it on your hardware target. In case it works, I would push it upstream. I did not zeroed the general-purpose and FPU registers. AFAIK there is no need in calling conventions to hand over zeroed registers, did you really need that to proceed? |
Instead of re-using the register values found in HCR_EL2 and CPTR_EL2 and setting single bits within them, define the complete content to prevent inconsistent hardware/hypervisor state. Ref genodelabs#4759
I will not be able to test this right away because of health issues. But will do in a week or so. |
@mickenx please take the time you need. There is no need to hurry up. Get well soon! |
It works! Thanks. |
@mickenx thanks for testing. |
Instead of re-using the register values found in HCR_EL2 and CPTR_EL2 and setting single bits within them, define the complete content to prevent inconsistent hardware/hypervisor state. Ref genodelabs#4759
Instead of re-using the register values found in HCR_EL2 and CPTR_EL2 and setting single bits within them, define the complete content to prevent inconsistent hardware/hypervisor state. Ref #4759
Merged to master. |
@mickenx has enabled a first version of Genode's hw kernel running on RK3588. Therefore, it was necessary to zero out HCR and CPTR of EL2. He has done this within the initial assembler code that is run more or less unconditionally. In the generic codebase we cannot do so, because we do not necessarily start in EL2 mode. I wonder whether it is enough to zero these two registers within bootstrap's high-level code in Platform::enable_mmu() at the right place.
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