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* first attempt * add support for verilog * fix error highlighting * update tree-siter-verilog * add screenshot * fix typo
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Original file line number | Diff line number | Diff line change |
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module nand_switch(a,b,out); | ||
input a,b; | ||
output out; | ||
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supply0 vss; | ||
supply1 vdd; | ||
wire net1; | ||
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wire foo; | ||
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pmos p1 (vdd,out,a); | ||
pmos p2 (vdd,out,b); | ||
nmos n1 (vss,net1,a); | ||
nmos n2 (net1,out,b==2); | ||
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endmodule |
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