pyGHDL.dom: improvements (#1848)

# New Features
 
* Translate null statements.
* Sequential procedure call.
 * Concurrent assert statement (but without condition)
    This needs either PSL translations or help from @tgingold to have partial elaboration to a PSL assert becomes a normal VHDL assertion like in VHDL-93.
* Translate sensitivity lists.
 
# Changes
 
* None
 
# Bug fixes
 
* Changes due to typo in pyVHDLModel for `Choises`.

pyGHDL/dom/Concurrent.py

@@ -57,6 +57,7 @@
     WaveformElement as VHDLModel_WaveformElement,
     ConcurrentSimpleSignalAssignment as VHDLModel_ConcurrentSimpleSignalAssignment,
     ConcurrentProcedureCall as VHDLModel_ConcurrentProcedureCall,
+    ConcurrentAssertStatement as VHDLModel_ConcurrentAssertStatement,
     Name,
     ConcurrentStatement,
     SequentialStatement,
@@ -258,10 +259,9 @@ def parse(cls, processNode: Iir, label: str, hasSensitivityList: bool) -> "Proce
 
         sensitivityList = None
         if hasSensitivityList:
-            pass
-            # FIXME: sensitity list
-            # sensitivityListNode = nodes.Get_Sensitivity_List(processNode)
-        #            print("sensi", GetIirKindOfNode(sensitivityListNode))
+            sensitivityList = []
+            for item in utils.list_iter(nodes.Get_Sensitivity_List(processNode)):
+                sensitivityList.append(GetNameOfNode(item))
 
         declaredItems = GetDeclaredItemsFromChainedNodes(nodes.Get_Declaration_Chain(processNode), "process", label)
         statements = GetSequentialStatementsFromChainedNodes(
@@ -719,3 +719,31 @@ def parse(cls, concurrentCallNode: Iir, label: str) -> "ConcurrentProcedureCall"
         parameterAssociations = GetParameterMapAspect(nodes.Get_Parameter_Association_Chain(callNode))
 
         return cls(concurrentCallNode, label, procedureName, parameterAssociations)
+
+
+@export
+class ConcurrentAssertStatement(VHDLModel_ConcurrentAssertStatement, DOMMixin):
+    def __init__(
+        self,
+        assertNode: Iir,
+        condition: ExpressionUnion,
+        message: ExpressionUnion = None,
+        severity: ExpressionUnion = None,
+        label: str = None,
+    ):
+        super().__init__(condition, message, severity, label)
+        DOMMixin.__init__(self, assertNode)
+
+    @classmethod
+    def parse(cls, assertNode: Iir, label: str) -> "ConcurrentAssertStatement":
+        from pyGHDL.dom._Translate import GetExpressionFromNode
+
+        # FIXME: how to get the condition?
+        # assertNode is a Psl_Assert_Directive
+        condition = None  # GetExpressionFromNode(nodes.Get_Assertion_Condition(assertNode))
+        messageNode = nodes.Get_Report_Expression(assertNode)
+        message = None if messageNode is nodes.Null_Iir else GetExpressionFromNode(messageNode)
+        severityNode = nodes.Get_Severity_Expression(assertNode)
+        severity = None if severityNode is nodes.Null_Iir else GetExpressionFromNode(severityNode)
+
+        return cls(assertNode, condition, message, severity, label)

pyGHDL/dom/Sequential.py

@@ -54,6 +54,7 @@
     SequentialProcedureCall as VHDLModel_SequentialProcedureCall,
     SequentialAssertStatement as VHDLModel_SequentialAssertStatement,
     SequentialReportStatement as VHDLModel_SequentialReportStatement,
+    NullStatement as VHDLModel_NullStatement,
     WaitStatement as VHDLModel_WaitStatement,
     Name,
     SequentialStatement,
@@ -423,11 +424,11 @@ def __init__(
     def parse(cls, callNode: Iir, label: str) -> "SequentialProcedureCall":
         from pyGHDL.dom._Translate import GetNameFromNode, GetParameterMapAspect
 
-        call = nodes.Get_Procedure_Call(callNode)
+        cNode = nodes.Get_Procedure_Call(callNode)
 
-        prefix = nodes.Get_Prefix(call)
+        prefix = nodes.Get_Prefix(cNode)
         procedureName = GetNameFromNode(prefix)
-        parameterAssociations = GetParameterMapAspect(nodes.Get_Parameter_Association_Chain(callNode))
+        parameterAssociations = GetParameterMapAspect(nodes.Get_Parameter_Association_Chain(cNode))
 
         return cls(callNode, procedureName, parameterAssociations, label)
 
@@ -481,6 +482,17 @@ def parse(cls, reportNode: Iir, label: str) -> "SequentialReportStatement":
         return cls(reportNode, message, severity, label)
 
 
+@export
+class NullStatement(VHDLModel_NullStatement, DOMMixin):
+    def __init__(
+        self,
+        waitNode: Iir,
+        label: str = None,
+    ):
+        super().__init__(label)
+        DOMMixin.__init__(self, waitNode)
+
+
 @export
 class WaitStatement(VHDLModel_WaitStatement, DOMMixin):
     def __init__(

pyGHDL/dom/_Translate.py

@@ -42,6 +42,8 @@
     SequentialAssertStatement,
     WaitStatement,
     SequentialSimpleSignalAssignment,
+    NullStatement,
+    SequentialProcedureCall,
 )
 from pyVHDLModel.SyntaxModel import (
     ConstraintUnion,
@@ -164,6 +166,7 @@
     GenericAssociationItem,
     PortAssociationItem,
     ParameterAssociationItem,
+    ConcurrentAssertStatement,
 )
 from pyGHDL.dom.Subprogram import Function, Procedure
 from pyGHDL.dom.Misc import Alias
@@ -920,11 +923,7 @@ def GetConcurrentStatementsFromChainedNodes(
         elif kind == nodes.Iir_Kind.For_Generate_Statement:
             yield ForGenerateStatement.parse(statement, label)
         elif kind == nodes.Iir_Kind.Psl_Assert_Directive:
-            print(
-                "[NOT IMPLEMENTED] PSL assert directive (label: '{label}') at line {line}".format(
-                    label=label, line=pos.Line
-                )
-            )
+            yield ConcurrentAssertStatement.parse(statement, label)
         else:
             raise DOMException(
                 "Unknown statement of kind '{kind}' in {entity} '{name}' at {file}:{line}:{column}.".format(
@@ -967,17 +966,13 @@ def GetSequentialStatementsFromChainedNodes(
         elif kind == nodes.Iir_Kind.Wait_Statement:
             yield WaitStatement.parse(statement, label)
         elif kind == nodes.Iir_Kind.Procedure_Call_Statement:
-            print(
-                "[NOT IMPLEMENTED] Procedure call (label: '{label}') at line {line}".format(label=label, line=pos.Line)
-            )
+            yield SequentialProcedureCall.parse(statement, label)
         elif kind == nodes.Iir_Kind.Report_Statement:
             yield SequentialReportStatement.parse(statement, label)
         elif kind == nodes.Iir_Kind.Assertion_Statement:
             yield SequentialAssertStatement.parse(statement, label)
         elif kind == nodes.Iir_Kind.Null_Statement:
-            print(
-                "[NOT IMPLEMENTED] null statement (label: '{label}') at line {line}".format(label=label, line=pos.Line)
-            )
+            yield NullStatement(statement, label)
         else:
             raise DOMException(
                 "Unknown statement of kind '{kind}' in {entity} '{name}' at {file}:{line}:{column}.".format(

pyGHDL/dom/requirements.txt

@@ -1,4 +1,4 @@
 -r ../libghdl/requirements.txt
 
-pyVHDLModel==0.11.5
+pyVHDLModel==0.12.0
 #https://github.com/VHDL/pyVHDLModel/archive/dev.zip#pyVHDLModel

testsuite/pyunit/Current.vhdl

@@ -94,6 +94,7 @@ begin
 				Q <= D after 10 ns;
 			else
 				Q <= std_logic_vector(unsigned(Q) + 1);
+				counter.increment(1);
 			end if;
 		end if;
 
@@ -133,6 +134,10 @@ begin
 
 	a <= b;
 
+	assert false;
+	assert false report "some error";
+	assert false severity warning;
+	assert false report "some note" severity note;
 
 	inst1: entity work.counter1(rtl)
 		generic map (
@@ -210,6 +215,11 @@ begin
 				constant G7 : boolean := False;
 			begin
 				inst: component Case5689Dummy;
+				process
+				begin
+					null;
+					wait;
+				end process;
 
 		when others =>
 				constant G8 : boolean := False;