testsuite/synth: add test for #1781

testsuite/synth/issue1781/imem.vhdl

@@ -0,0 +1,105 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity imem is
+  generic (
+    IMEM_BASE : std_ulogic_vector(31 downto 0) := x"00000000";
+    IMEM_SIZE : natural := 4*1024
+  );
+  port (
+    clk_i  : in  std_ulogic;
+    rden_i : in  std_ulogic;
+    wren_i : in  std_ulogic;
+    ben_i  : in  std_ulogic_vector(03 downto 0);
+    addr_i : in  std_ulogic_vector(31 downto 0);
+    data_i : in  std_ulogic_vector(31 downto 0);
+    data_o : out std_ulogic_vector(31 downto 0);
+    ack_o  : out std_ulogic
+  );
+end entity;
+
+architecture ok of imem is
+  signal addr : std_ulogic_vector(15 downto 0);
+  type ram_t is array(0 to 2**15-1) of std_ulogic_vector(31 downto 0);
+  signal acc_en : std_ulogic;
+  constant abb_c : std_logic_vector(31 downto 16) := (others=>'0');
+begin
+  addr <= addr_i(addr'left+2 downto 2); -- word aligned
+  acc_en <= addr_i(abb_c'range) ?= IMEM_BASE(abb_c'range);
+  process(clk_i)
+  variable memory : ram_t;
+  begin
+  if rising_edge(clk_i) then
+    if acc_en then
+      ack_o <= rden_i or wren_i;
+    end if;
+    if acc_en and wren_i then
+      for x in 0 to 3 loop
+        if ben_i(x) then
+          memory(to_integer(unsigned(addr)))((x+1)*8-1 downto x*8) := data_i((x+1)*8-1 downto x*8);
+        end if;
+      end loop;
+    end if;
+    if acc_en and rden_i then
+      data_o <= memory(to_integer(unsigned(addr)));
+    end if;
+  end if;
+  end process;
+end architecture;
+
+architecture notok of imem is
+  signal addr : std_ulogic_vector(15 downto 0);
+  type ram_t is array(0 to 2**15-1) of std_ulogic_vector(31 downto 0);
+  signal acc_en : std_ulogic;
+  constant abb_c : std_logic_vector(31 downto 16) := (others=>'0');
+begin
+  addr <= addr_i(addr'left+2 downto 2); -- word aligned
+  acc_en <= addr_i(abb_c'range) ?= IMEM_BASE(abb_c'range);
+  process(clk_i)
+  variable memory : ram_t;
+  begin
+  if rising_edge(clk_i) and acc_en='1' then
+    ack_o <= rden_i or wren_i;
+    if wren_i then
+      for x in 0 to 3 loop
+        if ben_i(x) then
+          memory(to_integer(unsigned(addr)))((x+1)*8-1 downto x*8) := data_i((x+1)*8-1 downto x*8);
+        end if;
+      end loop;
+    end if;
+    if rden_i then
+      data_o <= memory(to_integer(unsigned(addr)));
+    end if;
+  end if;
+  end process;
+end architecture;
+
+architecture neitherok of imem is
+    signal addr : std_ulogic_vector(15 downto 0);
+    type ram_t is array(0 to 2**15-1) of std_ulogic_vector(31 downto 0);
+    signal acc_en : std_ulogic;
+    constant abb_c : std_logic_vector(31 downto 16) := (others=>'0');
+  begin
+    addr <= addr_i(addr'left+2 downto 2); -- word aligned
+    acc_en <= addr_i(abb_c'range) ?= IMEM_BASE(abb_c'range);
+    process(clk_i)
+    variable memory : ram_t;
+    begin
+    if rising_edge(clk_i) then
+      if acc_en then
+        ack_o <= rden_i or wren_i;
+        if wren_i then
+          for x in 0 to 3 loop
+            if ben_i(x) then
+              memory(to_integer(unsigned(addr)))((x+1)*8-1 downto x*8) := data_i((x+1)*8-1 downto x*8);
+            end if;
+          end loop;
+        end if;
+        if rden_i then
+          data_o <= memory(to_integer(unsigned(addr)));
+        end if;
+      end if;
+    end if;
+    end process;
+  end architecture;

testsuite/synth/issue1781/imem2.vhdl

@@ -0,0 +1,104 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity imem2 is
+  generic (
+    IMEM_BASE : std_ulogic_vector(31 downto 0) := x"00000000"
+  );
+  port (
+    clk_i  : in  std_ulogic;
+    rden_i : in  std_ulogic;
+    wren_i : in  std_ulogic;
+    ben_i  : in  std_ulogic_vector(03 downto 0);
+    addr_i : in  std_ulogic_vector(31 downto 0);
+    data_i : in  std_ulogic_vector(31 downto 0);
+    data_o : out std_ulogic_vector(31 downto 0);
+    ack_o  : out std_ulogic
+  );
+end entity;
+
+architecture ok of imem2 is
+  signal addr : std_ulogic_vector(15 downto 0);
+  type ram_t is array(0 to 2**15-1) of std_ulogic_vector(31 downto 0);
+  signal acc_en : std_ulogic;
+  constant abb_c : std_logic_vector(31 downto 16) := (others=>'0');
+begin
+  addr <= addr_i(addr'left+2 downto 2); -- word aligned
+  acc_en <= addr_i(abb_c'range) ?= IMEM_BASE(abb_c'range);
+  process(clk_i)
+  variable memory : ram_t;
+  begin
+  if rising_edge(clk_i) then
+    if acc_en then
+      ack_o <= rden_i or wren_i;
+    end if;
+    if acc_en and wren_i then
+      for x in 0 to 3 loop
+        if ben_i(x) then
+          memory(to_integer(unsigned(addr)))((x+1)*8-1 downto x*8) := data_i((x+1)*8-1 downto x*8);
+        end if;
+      end loop;
+    end if;
+    if acc_en and rden_i then
+      data_o <= memory(to_integer(unsigned(addr)));
+    end if;
+  end if;
+  end process;
+end architecture;
+
+architecture notok of imem2 is
+  signal addr : std_ulogic_vector(7 downto 0);
+  type ram_t is array(0 to 2**8-1) of std_ulogic_vector(31 downto 0);
+  signal acc_en : std_ulogic;
+  constant abb_c : std_logic_vector(31 downto 16) := (others=>'0');
+begin
+  addr <= addr_i(addr'left+2 downto 2); -- word aligned
+  acc_en <= addr_i(abb_c'range) ?= IMEM_BASE(abb_c'range);
+  process(clk_i)
+  variable memory : ram_t;
+  begin
+  if rising_edge(clk_i) and acc_en='1' then
+    ack_o <= rden_i or wren_i;
+    if wren_i then
+      for x in 0 to 3 loop
+        if ben_i(x) then
+          memory(to_integer(unsigned(addr)))((x+1)*8-1 downto x*8) := data_i((x+1)*8-1 downto x*8);
+        end if;
+      end loop;
+    end if;
+    if rden_i then
+      data_o <= memory(to_integer(unsigned(addr)));
+    end if;
+  end if;
+  end process;
+end architecture;
+
+architecture neitherok of imem2 is
+    signal addr : std_ulogic_vector(15 downto 0);
+    type ram_t is array(0 to 2**15-1) of std_ulogic_vector(31 downto 0);
+    signal acc_en : std_ulogic;
+    constant abb_c : std_logic_vector(31 downto 16) := (others=>'0');
+  begin
+    addr <= addr_i(addr'left+2 downto 2); -- word aligned
+    acc_en <= addr_i(abb_c'range) ?= IMEM_BASE(abb_c'range);
+    process(clk_i)
+    variable memory : ram_t;
+    begin
+    if rising_edge(clk_i) then
+      if acc_en then
+        ack_o <= rden_i or wren_i;
+        if wren_i then
+          for x in 0 to 3 loop
+            if ben_i(x) then
+              memory(to_integer(unsigned(addr)))((x+1)*8-1 downto x*8) := data_i((x+1)*8-1 downto x*8);
+            end if;
+          end loop;
+        end if;
+        if rden_i then
+          data_o <= memory(to_integer(unsigned(addr)));
+        end if;
+      end if;
+    end if;
+    end process;
+  end architecture;

testsuite/synth/issue1781/imem2a.vhdl

@@ -0,0 +1,46 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity imem2a is
+  generic (
+    IMEM_BASE : std_ulogic_vector(31 downto 0) := x"00000000"
+  );
+  port (
+    clk_i  : in  std_ulogic;
+    rden_i : in  std_ulogic;
+    wren_i : in  std_ulogic;
+    ben_i  : in  std_ulogic_vector(01 downto 0);
+    addr_i : in  std_ulogic_vector(31 downto 0);
+    data_i : in  std_ulogic_vector(15 downto 0);
+    data_o : out std_ulogic_vector(15 downto 0);
+    ack_o  : out std_ulogic
+  );
+end entity;
+
+architecture notok of imem2a is
+  signal addr : std_ulogic_vector(7 downto 0);
+  type ram_t is array(0 to 2**8-1) of std_ulogic_vector(15 downto 0);
+  signal acc_en : std_ulogic;
+begin
+  addr <= addr_i(addr'left+2 downto 2); -- word aligned
+  acc_en <= '1';
+
+  process(clk_i)
+    variable memory : ram_t;
+  begin
+  if rising_edge(clk_i) and acc_en='1' then
+    ack_o <= rden_i or wren_i;
+    if wren_i then
+      for x in 0 to 1 loop
+        if ben_i(x) then
+          memory(to_integer(unsigned(addr)))((x+1)*8-1 downto x*8) := data_i((x+1)*8-1 downto x*8);
+        end if;
+      end loop;
+    end if;
+    if rden_i then
+      data_o <= memory(to_integer(unsigned(addr)));
+    end if;
+  end if;
+  end process;
+end architecture;

testsuite/synth/issue1781/simple2.vhdl

@@ -0,0 +1,31 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity simple2 is
+  port (
+    clk_i  : in  std_ulogic;
+    rden_i : in  std_ulogic;
+    wren_i : in  std_ulogic;
+    addr_i : in  std_ulogic_vector(7 downto 0);
+    data_i : in  std_ulogic_vector(15 downto 0);
+    data_o : out std_ulogic_vector(15 downto 0)
+  );
+end entity;
+
+architecture notok of simple2 is
+  type ram_t is array(0 to 2**8-1) of std_ulogic_vector(15 downto 0);
+begin
+  process(clk_i)
+    variable memory : ram_t;
+  begin
+    if rising_edge(clk_i) then
+      if wren_i = '1' then
+        memory(to_integer(unsigned(addr_i))) := data_i;
+      end if;
+      if rden_i = '1' then
+        data_o <= memory(to_integer(unsigned(addr_i)));
+      end if;
+    end if;
+  end process;
+end architecture;

testsuite/synth/issue1781/simple2_dc.vhdl

@@ -0,0 +1,34 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity simple2_dc is
+  port (
+    rclk_i : in  std_ulogic;
+    wclk_i : in  std_ulogic;
+    rden_i : in  std_ulogic;
+    wren_i : in  std_ulogic;
+    addr_i : in  std_ulogic_vector(7 downto 0);
+    data_i : in  std_ulogic_vector(15 downto 0);
+    data_o : out std_ulogic_vector(15 downto 0)
+  );
+end entity;
+
+architecture notok of simple2_dc is
+  type ram_t is array(0 to 2**8-1) of std_ulogic_vector(15 downto 0);
+begin
+  process(wclk_i, rclk_i)
+    variable memory : ram_t;
+  begin
+    if rising_edge(wclk_i) then
+      if wren_i = '1' then
+        memory(to_integer(unsigned(addr_i))) := data_i;
+      end if;
+    end if;
+    if rising_edge(rclk_i) then
+      if rden_i = '1' then
+        data_o <= memory(to_integer(unsigned(addr_i)));
+      end if;
+    end if;
+  end process;
+end architecture;

testsuite/synth/issue1781/simple3.vhdl

@@ -0,0 +1,25 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity imem2a is
+  port (
+    clk_i  : in  std_ulogic;
+    addr_i : in  std_ulogic_vector(30 downto 0);
+    data_i : in  std_ulogic_vector(15 downto 0);
+    data_o : out std_ulogic_vector(15 downto 0)
+  );
+end entity;
+
+architecture notok of imem2a is
+  type ram_t is array(0 to 2**8-1) of std_ulogic_vector(15 downto 0);
+begin
+  process(clk_i)
+    variable memory : ram_t;
+  begin
+    if rising_edge(clk_i) then
+      memory(to_integer(unsigned(addr_i))) := data_i;
+      data_o <= memory(to_integer(unsigned(addr_i)));
+    end if;
+  end process;
+end architecture;