Add testcase for issue2.

testsuite/gna/issue2/sortnet_OddEvenSort.vhdl

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+-- EMACS settings: -*-  tab-width: 2; indent-tabs-mode: t -*-
+-- vim: tabstop=2:shiftwidth=2:noexpandtab
+-- kate: tab-width 2; replace-tabs off; indent-width 2;
+-- 
+-- =============================================================================
+-- Authors:					Patrick Lehmann
+--
+-- Module:					Sorting Network: Odd-Even-Sort (Transposition)
+--
+-- Description:
+-- ------------------------------------
+--	TODO
+--
+-- License:
+-- =============================================================================
+-- Copyright 2007-2015 Technische Universitaet Dresden - Germany
+--										 Chair for VLSI-Design, Diagnostics and Architecture
+-- 
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+-- 
+--		http://www.apache.org/licenses/LICENSE-2.0
+-- 
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+-- =============================================================================
+
+library IEEE;
+use			IEEE.STD_LOGIC_1164.all;
+
+package vectors is
+	type		T_SLM								is array(NATURAL range <>, NATURAL range <>) of STD_LOGIC;
+end package;
+
+
+library IEEE;
+use			IEEE.STD_LOGIC_1164.all;
+use			IEEE.NUMERIC_STD.all;
+
+--library PoC;
+-- use			PoC.utils.all;
+--use			PoC.vectors.all;
+--use			PoC.components.all;
+use			work.vectors.all;
+
+
+entity sortnet_OddEvenSort is
+	generic (
+		INPUTS								: POSITIVE	:= 8;
+		KEY_BITS							: POSITIVE	:= 16;
+		DATA_BITS							: NATURAL		:= 16;
+		PIPELINE_STAGE_AFTER	: NATURAL		:= 2;
+		ADD_OUTPUT_REGISTERS	: BOOLEAN		:= TRUE;
+		INVERSE								: BOOLEAN		:= FALSE
+	);
+	port (
+		Clock				: in	STD_LOGIC;
+		Reset				: in	STD_LOGIC;
+
+		DataInputs	: in	T_SLM(INPUTS - 1 downto 0, DATA_BITS - 1 downto 0);
+		DataOutputs	: out	T_SLM(INPUTS - 1 downto 0, DATA_BITS - 1 downto 0)
+	);
+end entity;
+
+
+architecture rtl of sortnet_OddEvenSort is
+	constant C_VERBOSE	: BOOLEAN	:= FALSE;
+
+	constant STAGES			: POSITIVE		:= INPUTS;
+
+	subtype T_DATA			is STD_LOGIC_VECTOR(DATA_BITS - 1 downto 0);
+	type T_DATA_VECTOR	is array(NATURAL range <>) of T_DATA;
+	type T_DATA_MATRIX	is array(NATURAL range <>, NATURAL range <>) of T_DATA;
+
+	function to_dv(slm : T_SLM) return T_DATA_VECTOR is
+		variable Result	: T_DATA_VECTOR(slm'range(1));
+	begin
+		for i in slm'range(1) loop
+			for j in slm'high(2) downto slm'low(2) loop
+				Result(i)(j)	:= slm(i, j);
+			end loop;
+		end loop;
+		return Result;
+	end function;
+
+	function to_slm(dv : T_DATA_VECTOR) return T_SLM is
+		variable Result	: T_SLM(dv'range, T_DATA'range);
+	begin
+		for i in dv'range loop
+			for j in T_DATA'range loop
+				Result(i, j)	:= dv(i)(j);
+			end loop;
+		end loop;
+		return Result;
+	end function;
+
+	function mux(sel : STD_LOGIC; slv0 : STD_LOGIC_VECTOR; slv1 : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
+	begin
+		return (slv0 and not (slv0'range => sel)) or (slv1 and (slv1'range => sel));
+	end function;
+
+	signal DataInputVector	: T_DATA_VECTOR(INPUTS - 1 downto 0);
+	signal DataInputMatrix	: T_DATA_MATRIX(STAGES - 1 downto 0, INPUTS - 1 downto 0);
+	signal DataOutputMatrix	: T_DATA_MATRIX(STAGES - 1 downto 0, INPUTS - 1 downto 0);
+	signal DataOutputVector	: T_DATA_VECTOR(INPUTS - 1 downto 0);
+
+begin
+	DataInputVector	<= to_dv(DataInputs);
+
+	genInputs : for i in 0 to INPUTS - 1 generate
+		DataInputMatrix(0, i)	<= DataInputVector(i);
+	end generate;
+
+	genConStage : for stage in 0 to STAGES - 2 generate
+		constant INSERT_REGISTER : BOOLEAN	:= ((PIPELINE_STAGE_AFTER > 0) and (stage mod PIPELINE_STAGE_AFTER = 0));
+	begin
+		genCon : for i in 0 to INPUTS - 1 generate
+			genPipeStage : if (INSERT_REGISTER = TRUE) generate
+				DataInputMatrix(stage + 1, i)	<= DataOutputMatrix(stage, i)	when rising_edge(Clock);
+			end generate;
+			genNoPipeStage : if (INSERT_REGISTER = FALSE) generate
+				DataInputMatrix(stage + 1, i)	<= DataOutputMatrix(stage, i);
+			end generate;
+		end generate;
+	end generate;
+
+	genSwitchStage : for stage in 0 to STAGES - 1 generate
+	begin
+		genEven : if (stage mod 2 = 0) generate
+			genEvenSwitch : for i in 0 to (INPUTS / 2) - 1 generate
+				signal DataIn0		: STD_LOGIC_VECTOR(DATA_BITS - 1 downto 0);
+				signal DataIn1		: STD_LOGIC_VECTOR(DATA_BITS - 1 downto 0);
+
+				signal Greater		: STD_LOGIC;
+				signal Switch			: STD_LOGIC;
+			begin
+				DataIn0		<= DataInputMatrix(stage, 2 * i);
+				DataIn1		<= DataInputMatrix(stage, 2 * i + 1);
+
+				Greater		<= '1' when (unsigned(DataIn0(KEY_BITS - 1 downto 0)) > unsigned(DataIn1(KEY_BITS - 1 downto 0))) else '0';
+				Switch		<= Greater;
+
+				DataOutputMatrix(stage, 2 * i)			<= mux(Switch, DataIn0, DataIn1);
+				DataOutputMatrix(stage, 2 * i + 1)	<= mux(Switch, DataIn1, DataIn0);
+			end generate;
+		end generate;
+		genOdd : if (stage mod 2 = 1) generate
+			DataOutputMatrix(stage, 0)					<= DataInputMatrix(stage, 0);
+			DataOutputMatrix(stage, INPUTS - 1)	<= DataInputMatrix(stage, INPUTS - 1);
+
+			genOddSwitch : for i in 0 to ((INPUTS - 1) / 2) - 1 generate
+				signal DataIn0		: STD_LOGIC_VECTOR(DATA_BITS - 1 downto 0);
+				signal DataIn1		: STD_LOGIC_VECTOR(DATA_BITS - 1 downto 0);
+
+				signal Greater		: STD_LOGIC;
+				signal Switch			: STD_LOGIC;
+			begin
+				DataIn0		<= DataInputMatrix(stage, 2 * i + 1);
+				DataIn1		<= DataInputMatrix(stage, 2 * i + 2);
+
+				Greater		<= '1' when (unsigned(DataIn0(KEY_BITS - 1 downto 0)) > unsigned(DataIn1(KEY_BITS - 1 downto 0))) else '0';
+				Switch		<= Greater;
+
+				DataOutputMatrix(stage, 2 * i + 1)	<= mux(Switch, DataIn0, DataIn1);
+				DataOutputMatrix(stage, 2 * i + 2)	<= mux(Switch, DataIn1, DataIn0);
+			end generate;
+		end generate;
+	end generate;
+
+	genOutputs : for i in 0 to INPUTS - 1 generate
+		DataOutputVector(i)		<= DataOutputMatrix(STAGES - 1, i);
+	end generate;
+
+	genOutReg : if (ADD_OUTPUT_REGISTERS = TRUE) generate
+		DataOutputs	<= to_slm(DataOutputVector)	when rising_edge(Clock);
+	end generate;
+	genNoOutReg : if (ADD_OUTPUT_REGISTERS = FALSE) generate
+		DataOutputs	<= to_slm(DataOutputVector);
+	end generate;
+end architecture;

testsuite/gna/issue2/sortnet_OddEvenSort_tb.vhdl

@@ -0,0 +1,158 @@
+-- EMACS settings: -*-  tab-width: 2; indent-tabs-mode: t -*-
+-- vim: tabstop=2:shiftwidth=2:noexpandtab
+-- kate: tab-width 2; replace-tabs off; indent-width 2;
+-- 
+-- =============================================================================
+-- Authors:					Patrick Lehmann
+--
+-- Testbench:				Sorting Network: Odd-Even-Sort (Transposition)
+--
+-- Description:
+-- ------------------------------------
+--	TODO
+--
+-- License:
+-- =============================================================================
+-- Copyright 2007-2015 Technische Universitaet Dresden - Germany
+--										 Chair for VLSI-Design, Diagnostics and Architecture
+-- 
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+-- 
+--		http://www.apache.org/licenses/LICENSE-2.0
+-- 
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+-- =============================================================================
+
+
+library IEEE;
+use			IEEE.STD_LOGIC_1164.all;
+use			IEEE.NUMERIC_STD.all;
+
+--library PoC;
+--use			PoC.utils.all;
+--use			PoC.vectors.all;
+
+use			work.vectors.all;
+
+-- library OSVVM;
+-- use			OSVVM.RandomPkg.all;
+
+
+entity sortnet_OddEvenSort_tb is
+end entity;
+
+
+architecture tb of sortnet_OddEvenSort_tb is
+	constant INPUTS				: POSITIVE	:= 8;
+	constant KEY_BITS			: POSITIVE	:= 8;
+	constant DATA_BITS		: POSITIVE	:= 8;
+
+	subtype T_KEY					is STD_LOGIC_VECTOR(KEY_BITS - 1 downto 0);
+
+	type T_KEY_VECTOR			is array(NATURAL range <>) of T_KEY;
+
+	function to_kv(slm : T_SLM) return T_KEY_VECTOR is
+		variable Result	: T_KEY_VECTOR(slm'range(1));
+	begin
+		for i in slm'high(1) downto slm'low(1) loop
+			for j in slm'high(2) downto slm'low(2) loop
+				Result(i)(j)	:= slm(i, j);
+			end loop;
+		end loop;
+		return Result;
+	end function;
+
+	function to_slm(kv : T_KEY_VECTOR) return T_SLM is
+		variable Result	: T_SLM(kv'range, T_KEY'range);
+	begin
+		for i in kv'range loop
+			for j in T_KEY'range loop
+				Result(i, j)	:= kv(i)(j);
+			end loop;
+		end loop;
+		return Result;
+	end function;
+
+	constant CLOCK_PERIOD			: TIME				:= 10 ns;
+	signal Clock							: STD_LOGIC		:= '1';
+
+	signal KeyInputVector			: T_KEY_VECTOR(INPUTS - 1 downto 0)		:= (others => (others => '0'));
+
+	signal DataInputMatrix		: T_SLM(INPUTS - 1 downto 0, DATA_BITS - 1 downto 0);
+	signal DataOutputMatrix		: T_SLM(INPUTS - 1 downto 0, DATA_BITS - 1 downto 0);
+
+	signal KeyOutputVector		: T_KEY_VECTOR(INPUTS - 1 downto 0);
+
+	signal StopSimulation			: STD_LOGIC		:= '0';
+begin
+
+	Clock	<= Clock xnor StopSimulation after CLOCK_PERIOD;
+
+	process
+		-- variable RandomVar : RandomPType;								-- protected type from RandomPkg
+	begin
+		-- RandomVar.InitSeed(RandomVar'instance_name);		-- Generate initial seeds
+
+		wait until rising_edge(Clock);
+
+		for i in 0 to 63 loop
+			wait until rising_edge(Clock);
+
+			for j in 0 to INPUTS - 1 loop
+				-- KeyInputVector(j)	<= RandomVar.RandSlv(0, 255), KEY_BITS);
+				KeyInputVector(j)	<= std_logic_vector(unsigned(KeyInputVector(j)) + i + j);
+			end loop;
+		end loop;
+
+		for i in 0 to 7 loop
+			wait until rising_edge(Clock);
+		end loop;
+
+		StopSimulation		<= '1';
+		wait;
+	end process;
+
+	DataInputMatrix		<= to_slm(KeyInputVector);
+
+	sort : entity work.sortnet_OddEvenSort
+		generic map (
+			INPUTS								=> INPUTS,
+			KEY_BITS							=> KEY_BITS,
+			DATA_BITS							=> DATA_BITS,
+			PIPELINE_STAGE_AFTER	=> 2,
+			ADD_OUTPUT_REGISTERS	=> TRUE
+		)
+		port map (
+			Clock				=> Clock,
+			Reset				=> '0',
+
+			DataInputs	=> DataInputMatrix,
+			DataOutputs	=> DataOutputMatrix
+		);
+
+	KeyOutputVector	<= to_kv(DataOutputMatrix);
+
+	process
+		variable	Check		: BOOLEAN;
+	begin
+		for i in 0 to 5 loop
+			wait until rising_edge(Clock);
+		end loop;
+
+		for i in 0 to 63 loop
+			Check		:= TRUE;
+			for j in 0 to INPUTS - 2 loop
+				Check	:= Check and (KeyOutputVector(j) <= KeyOutputVector(j + 1));
+			end loop;
+			assert Check report "ERROR: " severity ERROR;
+		end loop;
+
+		wait;
+	end process;
+end architecture;

testsuite/gna/issue2/testsuite.sh

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+#! /bin/sh
+
+. ../../testenv.sh
+
+GHDL_STD_FLAGS=--std=08
+GHDL_FLAGS=--work=test
+
+analyze sortnet_OddEvenSort.vhdl
+analyze sortnet_OddEvenSort_tb.vhdl
+elab_simulate --syn-binding sortnet_OddEvenSort_tb
+
+clean test
+
+echo "Test successful"