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library ieee; | ||
use ieee.std_logic_1164.all; | ||
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entity sequencer is | ||
generic ( | ||
seq : string | ||
); | ||
port ( | ||
clk : in std_logic; | ||
data : out std_logic | ||
); | ||
end entity sequencer; | ||
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architecture rtl of sequencer is | ||
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signal index : natural := seq'low; | ||
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function to_bit (a : in character) return std_logic is | ||
variable ret : std_logic; | ||
begin | ||
case a is | ||
when '0' | '_' => ret := '0'; | ||
when '1' | '-' => ret := '1'; | ||
when others => ret := 'X'; | ||
end case; | ||
return ret; | ||
end function to_bit; | ||
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begin | ||
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process (clk) is | ||
begin | ||
if rising_edge(clk) then | ||
if (index < seq'high) then | ||
index <= index + 1; | ||
end if; | ||
end if; | ||
end process; | ||
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data <= to_bit(seq(index)); | ||
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end architecture rtl; | ||
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library ieee; | ||
use ieee.std_logic_1164.all; | ||
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library ieee; | ||
use ieee.std_logic_1164.all; | ||
use ieee.numeric_std.all; | ||
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entity issue is | ||
port ( | ||
clk : in std_logic | ||
); | ||
end entity issue; | ||
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architecture psl of issue is | ||
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signal a, b : std_logic; | ||
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begin | ||
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-- 012345678901 | ||
SEQ_A : entity work.sequencer generic map ("__-___-_____") port map (clk, a); | ||
SEQ_B : entity work.sequencer generic map ("___-_____-__") port map (clk, b); | ||
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-- All is sensitive to rising edge of clk | ||
default clock is rising_edge(clk); | ||
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-- This assertion should hold | ||
INF_a : assert always {a} |=> {not b[*0 to inf]; b}; | ||
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INF_b : assert always {a} |=> {not b[*]; b}; | ||
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end architecture psl; | ||
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library ieee; | ||
use ieee.std_logic_1164.all; | ||
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use std.env.all; | ||
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entity test_issue is | ||
end entity test_issue; | ||
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architecture sim of test_issue is | ||
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signal clk : std_logic := '1'; | ||
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begin | ||
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clk <= not clk after 500 ps; | ||
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DUT : entity work.issue(psl) port map (clk); | ||
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-- stop simulation after 30 cycles | ||
process | ||
variable index : natural := 29; | ||
begin | ||
loop | ||
wait until rising_edge(clk); | ||
index := index - 1; | ||
exit when index = 0; | ||
end loop; | ||
stop(0); | ||
end process; | ||
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end architecture sim; |
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#! /bin/sh | ||
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. ../../testenv.sh | ||
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export GHDL_STD_FLAGS=--std=08 | ||
analyze issue.vhdl | ||
elab_simulate issue | ||
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clean | ||
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echo "Test successful" |