testsuite/gna: add a test for #1625

testsuite/gna/issue1625/level0.vhdl

@@ -0,0 +1,41 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std_unsigned.all;
+
+entity level0 is
+end entity level0;
+
+architecture synthesis of level0 is
+
+   signal clk       : std_logic;
+   signal rst       : std_logic;
+   signal src_reg   : std_logic_vector(3 downto 0);
+   signal src_val   : std_logic_vector(15 downto 0);
+   signal dst_reg   : std_logic_vector(3 downto 0);
+   signal dst_val   : std_logic_vector(15 downto 0);
+   signal flags_out : std_logic_vector(15 downto 0);
+   signal flags_we  : std_logic;
+   signal flags_in  : std_logic_vector(15 downto 0); 
+   signal reg_we    : std_logic;
+   signal reg_addr  : std_logic_vector(3 downto 0);
+   signal reg_val   : std_logic_vector(15 downto 0);
+
+begin
+
+   inst : entity work.level1
+      port map (
+         clk_i       => clk,
+         rst_i       => rst,
+         src_reg_i   => src_reg,
+         src_val_o   => src_val,
+         dst_reg_i   => dst_reg,
+         dst_val_o   => dst_val,
+         flags_o     => flags_out,
+         flags_we_i  => flags_we,
+         flags_i     => flags_in,
+         reg_we_i    => reg_we,
+         reg_addr_i  => reg_addr,
+         reg_val_i   => reg_val
+      );
+
+end architecture synthesis;

testsuite/gna/issue1625/level1.vhdl

@@ -0,0 +1,44 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std_unsigned.all;
+
+entity level1 is
+   port (
+      clk_i      : in  std_logic;
+      rst_i      : in  std_logic;
+      src_reg_i  : in  std_logic_vector(3 downto 0);
+      src_val_o  : out std_logic_vector(15 downto 0);
+      dst_reg_i  : in  std_logic_vector(3 downto 0);
+      dst_val_o  : out std_logic_vector(15 downto 0);
+      flags_o    : out std_logic_vector(15 downto 0);
+      flags_we_i : in  std_logic;
+      flags_i    : in  std_logic_vector(15 downto 0);
+      reg_we_i   : in  std_logic;
+      reg_addr_i : in  std_logic_vector(3 downto 0);
+      reg_val_i  : in  std_logic_vector(15 downto 0)
+   );
+end entity level1;
+
+architecture synthesis of level1 is
+
+   signal sr : std_logic_vector(15 downto 0);
+   signal dst_val_lower : std_logic_vector(15 downto 0);
+
+begin
+
+   inst : entity work.level2
+      generic map (
+         G_ADDR_SIZE => 11,
+         G_DATA_SIZE => 16
+      )
+      port map (
+         clk_i     => clk_i,
+         rst_i     => rst_i,
+         rd_addr_i => sr(15 downto 8) & dst_reg_i(2 downto 0),
+         rd_data_o => dst_val_lower,
+         wr_addr_i => sr(15 downto 8) & reg_addr_i(2 downto 0),
+         wr_data_i => reg_val_i,
+         wr_en_i   => reg_we_i and not reg_addr_i(3)
+      ); -- i_ram_lower_dst
+
+end architecture synthesis;

testsuite/gna/issue1625/level2.vhdl

@@ -0,0 +1,27 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std_unsigned.all;
+
+entity level2 is
+   generic (
+      G_ADDR_SIZE : integer;
+      G_DATA_SIZE : integer
+   );
+   port (
+      clk_i         : in  std_logic;
+      rst_i         : in  std_logic;
+      -- Read interface
+      rd_addr_i     : in  std_logic_vector(G_ADDR_SIZE-1 downto 0);
+      rd_data_o     : out std_logic_vector(G_DATA_SIZE-1 downto 0);
+      -- Write interface
+      wr_addr_i     : in  std_logic_vector(G_ADDR_SIZE-1 downto 0);
+      wr_data_i     : in  std_logic_vector(G_DATA_SIZE-1 downto 0);
+      wr_en_i       : in  std_logic
+   );
+end entity level2;
+
+architecture synthesis of level2 is
+
+begin
+
+end architecture synthesis;

testsuite/gna/issue1625/testsuite.sh

@@ -0,0 +1,15 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+export GHDL_STD_FLAGS=--std=08
+analyze level2.vhdl
+analyze level1.vhdl
+elab_simulate level1
+
+analyze level0.vhdl
+elab_simulate level0
+
+clean
+
+echo "Test successful"