Add testcase for alignment issue on windows.

ghdl · Jan 9, 2016 · a6b81ad · a6b81ad
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diff --git a/testsuite/gna/bug035/arith_prng.vhdl b/testsuite/gna/bug035/arith_prng.vhdl
@@ -0,0 +1,274 @@
+-- EMACS settings: -*-  tab-width: 2; indent-tabs-mode: t -*-
+-- vim: tabstop=2:shiftwidth=2:noexpandtab
+-- kate: tab-width 2; replace-tabs off; indent-width 2;
+-- 
+-- ============================================================================================================================================================
+-- Module:					Pseudo-Random Number Generator (PRNG).
+-- 
+-- Authors:					Martin Zabel
+--									Patrick Lehmann
+-- 
+-- Description:
+-- ------------------------------------
+--		The number sequence includes the value all-zeros, but not all-ones.
+--		Synchronized Reset is used.
+--
+-- License:
+-- ============================================================================================================================================================
+-- Copyright 2007-2014 Technische Universitaet Dresden - Germany
+--										 Chair for VLSI-Design, Diagnostics and Architecture
+-- 
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+-- 
+--		http://www.apache.org/licenses/LICENSE-2.0
+-- 
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+-- ============================================================================================================================================================
+
+library ieee;
+use			ieee.std_logic_1164.all;
+use			ieee.numeric_std.all;
+
+library PoC;
+use			PoC.utils.all;
+
+
+entity arith_prng is
+	generic (
+		BITS : positive;
+		SEED : std_logic_vector := "0"
+	);
+	port (
+		clk	 : in	std_logic;
+		rst	 : in	std_logic;														-- reset value to initial seed
+		got	 : in	std_logic;														-- the current value has been got, and a new value should be calculated
+		val	 : out std_logic_vector(BITS - 1 downto 0)	-- the pseudo-random number
+	);
+end arith_prng;
+
+
+architecture rtl of arith_prng is
+	subtype T_TAPPOSITION				is T_NATVEC(0 TO 4);
+	type T_TAPPOSITION_VECTOR		is array (natural range <>) of T_TAPPOSITION;
+
+	-- Tap positions are taken from Xilinx Application Note 052 (XAPP052)
+	constant C_TAPPOSITION_LIST : T_TAPPOSITION_VECTOR(3 to 168) := (
+		3		=> (0 => 2,												others => 0),
+		4		=> (0 => 3,												others => 0),
+		5		=> (0 => 3,												others => 0),
+		6		=> (0 => 5,												others => 0),
+		7		=> (0 => 6,												others => 0),
+		8		=> (0 => 6,		1 => 5,		2 => 4, 	others => 0),
+		9		=> (0 => 5,												others => 0),
+		10	=> (0 => 7,												others => 0),
+		11	=> (0 => 9,												others => 0),
+		12	=> (0 => 6,		1 => 4,		2 => 1, 	others => 0),
+		13	=> (0 => 4,		1 => 3,		2 => 1, 	others => 0),
+		14	=> (0 => 5,		1 => 3,		2 => 1, 	others => 0),
+		15	=> (0 => 14,											others => 0),
+		16	=> (0 => 15,	1 => 13,	2 => 4,		others => 0),
+		17	=> (0 => 14,											others => 0),
+		18	=> (0 => 11,											others => 0),
+		19	=> (0 => 6,		1 => 2,		2 => 1, 	others => 0),
+		20	=> (0 => 17,											others => 0),
+		21	=> (0 => 19,											others => 0),
+		22	=> (0 => 21,											others => 0),
+		23	=> (0 => 18,											others => 0),
+		24	=> (0 => 23,	1 => 22,	2 => 17,	others => 0),
+		25	=> (0 => 22,											others => 0),
+		26	=> (0 => 6,		1 => 2,		2 => 1,		others => 0),
+		27	=> (0 => 5,		1 => 2,		2 => 1, 	others => 0),
+		28	=> (0 => 25,											others => 0),
+		29	=> (0 => 27,											others => 0),
+		30	=> (0 => 6,		1 => 4,		2 => 1,		others => 0),
+		31	=> (0 => 28,											others => 0),
+		32	=> (0 => 22,	1 => 2,		2 => 1, 	others => 0),
+		33	=> (0 => 2,												others => 0),
+		34	=> (0 => 27,	1 => 2,		2 => 1, 	others => 0),
+		35	=> (0 => 33,											others => 0),
+		36	=> (0 => 25,											others => 0),
+		37	=> (0 => 5,		1 => 4,		2 => 3,	3 => 2,	4 => 1),
+		38	=> (0 => 6,		1 => 5,		2 => 1,		others => 0),
+		39	=> (0 => 35,											others => 0),
+		40	=> (0 => 38,	1 => 21,	2 => 19,	others => 0),
+		41	=> (0 => 38,											others => 0),
+		42	=> (0 => 41,	1 => 20,	2 => 19,	others => 0),
+		43	=> (0 => 42,	1 => 38,	2 => 37,	others => 0),
+		44	=> (0 => 43,	1 => 18,	2 => 17,	others => 0),
+		45	=> (0 => 44,	1 => 42,	2 => 41,	others => 0),
+		46	=> (0 => 45,	1 => 26,	2 => 25,	others => 0),
+		47	=> (0 => 42,											others => 0),
+		48	=> (0 => 47,	1 => 21,	2 => 20,	others => 0),
+		49	=> (0 => 4,												others => 0),
+		50	=> (0 => 49,	1 => 24,	2 => 23,	others => 0),
+		51	=> (0 => 50,	1 => 36,	2 => 35,	others => 0),
+		52	=> (0 => 49,											others => 0),
+		53	=> (0 => 52,	1 => 38,	2 => 37,	others => 0),
+		54	=> (0 => 53,	1 => 18,	2 => 17,	others => 0),
+		55	=> (0 => 31,											others => 0),
+		56	=> (0 => 55,	1 => 35,	2 => 34,	others => 0),
+		57	=> (0 => 5,												others => 0),
+		58	=> (0 => 39,											others => 0),
+		59	=> (0 => 58,	1 => 38,	2 => 37,	others => 0),
+		60	=> (0 => 59,											others => 0),
+		61	=> (0 => 60,	1 => 46,	2 => 45,	others => 0),
+		62	=> (0 => 61,	1 => 6,		2 => 5,		others => 0),
+		63	=> (0 => 62,											others => 0),
+		64	=> (0 => 63,	1 => 61,	2 => 60,	others => 0),
+		65	=> (0 => 47,											others => 0),
+		66	=> (0 => 65,	1 => 57,	2 => 56,	others => 0),
+		67	=> (0 => 66,	1 => 58,	2 => 57,	others => 0),
+		68	=> (0 => 59,											others => 0),
+		69	=> (0 => 67,	1 => 42,	2 => 40,	others => 0),
+		70	=> (0 => 69,	1 => 55,	2 => 54,	others => 0),
+		71	=> (0 => 65,											others => 0),
+		72	=> (0 => 66,	1 => 25,	2 => 19,	others => 0),
+		73	=> (0 => 48,											others => 0),
+		74	=> (0 => 73,	1 => 59,	2 => 58,	others => 0),
+		75	=> (0 => 74,	1 => 65,	2 => 64,	others => 0),
+		76	=> (0 => 75,	1 => 41,	2 => 40,	others => 0),
+		77	=> (0 => 76,	1 => 47,	2 => 46,	others => 0),
+		78	=> (0 => 77,	1 => 59,	2 => 58,	others => 0),
+		79	=> (0 => 7,												others => 0),
+		80	=> (0 => 79,	1 => 43,	2 => 42,	others => 0),
+		81	=> (0 => 77,											others => 0),
+		82	=> (0 => 79,	1 => 47,	2 => 44,	others => 0),
+		83	=> (0 => 82,	1 => 38,	2 => 37,	others => 0),
+		84	=> (0 => 71,											others => 0),
+		85	=> (0 => 84,	1 => 58,	2 => 57,	others => 0),
+		86	=> (0 => 85,	1 => 74,	2 => 73,	others => 0),
+		87	=> (0 => 74,											others => 0),
+		88	=> (0 => 87,	1 => 17,	2 => 16,	others => 0),
+		89	=> (0 => 51,											others => 0),
+		90	=> (0 => 89,	1 => 72,	2 => 71,	others => 0),
+		91	=> (0 => 90,	1 => 8,		2 => 7,		others => 0),
+		92	=> (0 => 91,	1 => 80,	2 => 79,	others => 0),
+		93	=> (0 => 91,											others => 0),
+		94	=> (0 => 73,											others => 0),
+		95	=> (0 => 84,											others => 0),
+		96	=> (0 => 94,	1 => 49,	2 => 47,	others => 0),
+		97	=> (0 => 91,											others => 0),
+		98	=> (0 => 87,											others => 0),
+		99	=> (0 => 97,	1 => 54,	2 => 52,	others => 0),
+		100	=> (0 => 63,											others => 0),
+		101	=> (0 => 100,	1 => 95,	2 => 94,	others => 0),
+		102	=> (0 => 101,	1 => 36,	2 => 35,	others => 0),
+		103	=> (0 => 94,											others => 0),
+		104	=> (0 => 103,	1 => 94,	2 => 93,	others => 0),
+		105	=> (0 => 89,											others => 0),
+		106	=> (0 => 91,											others => 0),
+		107	=> (0 => 105,	1 => 44,	2 => 42,	others => 0),
+		108	=> (0 => 77,											others => 0),
+		109	=> (0 => 108,	1 => 103,	2 => 102, others => 0),
+		110	=> (0 => 109,	1 => 98,	2 => 97,	others => 0),
+		111	=> (0 => 101,											others => 0),
+		112	=> (0 => 110,	1 => 69,	2 => 67,	others => 0),
+		113	=> (0 => 104,											others => 0),
+		114	=> (0 => 113,	1 => 33,	2 => 32,	others => 0),
+		115	=> (0 => 114,	1 => 101,	2 => 100, others => 0),
+		116	=> (0 => 115,	1 => 46,	2 => 45,	others => 0),
+		117	=> (0 => 115,	1 => 99,	2 => 97,	others => 0),
+		118	=> (0 => 85,											others => 0),
+		119	=> (0 => 111,											others => 0),
+		120	=> (0 => 113,	1 => 9,		2 => 2,		others => 0),
+		121	=> (0 => 103,											others => 0),
+		122	=> (0 => 121,	1 => 63,	2 => 62,	others => 0),
+		123	=> (0 => 121,											others => 0),
+		124	=> (0 => 87,											others => 0),
+		125	=> (0 => 124,	1 => 18,	2 => 17,	others => 0),
+		126	=> (0 => 125,	1 => 90,	2 => 89,	others => 0),
+		127	=> (0 => 126,											others => 0),
+		128	=> (0 => 126,	1 => 101,	2 => 99,	others => 0),
+		129	=> (0 => 124,											others => 0),
+		130	=> (0 => 127,											others => 0),
+		131	=> (0 => 130,	1 => 84,	2 => 83,	others => 0),
+		132	=> (0 => 103,											others => 0),
+		133	=> (0 => 132,	1 => 82,	2 => 81,	others => 0),
+		134	=> (0 => 77,											others => 0),
+		135	=> (0 => 124,											others => 0),
+		136	=> (0 => 135,	1 => 11,	2 => 10,	others => 0),
+		137	=> (0 => 116,											others => 0),
+		138	=> (0 => 137,	1 => 131,	2 => 130, others => 0),
+		139	=> (0 => 136,	1 => 134,	2 => 131, others => 0),
+		140	=> (0 => 111,											others => 0),
+		141	=> (0 => 140,	1 => 110,	2 => 109, others => 0),
+		142	=> (0 => 121,											others => 0),
+		143	=> (0 => 142,	1 => 123,	2 => 122, others => 0),
+		144	=> (0 => 143,	1 => 75,	2 => 74,	others => 0),
+		145	=> (0 => 93,											others => 0),
+		146	=> (0 => 145,	1 => 87,	2 => 86,	others => 0),
+		147	=> (0 => 146,	1 => 110,	2 => 109, others => 0),
+		148	=> (0 => 121,											others => 0),
+		149	=> (0 => 148,	1 => 40,	2 => 39,	others => 0),
+		150	=> (0 => 97,											others => 0),
+		151	=> (0 => 148,											others => 0),
+		152	=> (0 => 151,	1 => 87,	2 => 86,	others => 0),
+		153	=> (0 => 152,											others => 0),
+		154	=> (0 => 152,	1 => 27,	2 => 25,	others => 0),
+		155	=> (0 => 154,	1 => 124,	2 => 123, others => 0),
+		156	=> (0 => 155,	1 => 41,	2 => 40,	others => 0),
+		157	=> (0 => 156,	1 => 131,	2 => 130, others => 0),
+		158	=> (0 => 157,	1 => 132,	2 => 131, others => 0),
+		159	=> (0 => 128,											others => 0),
+		160	=> (0 => 159,	1 => 142,	2 => 141, others => 0),
+		161	=> (0 => 143,											others => 0),
+		162	=> (0 => 161,	1 => 75,	2 => 74,	others => 0),
+		163	=> (0 => 162,	1 => 104,	2 => 103, others => 0),
+		164	=> (0 => 163,	1 => 151,	2 => 150, others => 0),
+		165	=> (0 => 164,	1 => 135,	2 => 134, others => 0),
+		166	=> (0 => 165,	1 => 128,	2 => 127, others => 0),
+		167	=> (0 => 161,											others => 0),
+		168	=> (0 => 166,	1 => 153,	2 => 151, others => 0)
+	);
+
+	constant C_TAPPOSITIONS	: T_TAPPOSITION		:= C_TAPPOSITION_LIST(BITS);
+
+	-- The current value
+	signal bit1_nxt	: std_logic;
+	signal val_r		: std_logic_vector(BITS downto 1)		:= resize(SEED, BITS);
+
+begin	-- rtl
+	assert ((3 <= BITS) and (BITS <= 168)) report "Width not yet supported." severity failure;
+
+	-----------------------------------------------------------------------------
+	-- Datapath
+	-----------------------------------------------------------------------------
+	-- XNOR used so that all-zero is valid and all-one is forbidden.
+	process(val_r)
+		variable temp : std_logic;
+	begin
+		temp			:= val_r(val_r'left);
+		for i in 0 to 4 loop
+			if (C_TAPPOSITIONS(i) > 0) then
+				temp	:= temp xnor val_r(C_TAPPOSITIONS(i));
+			end if;
+		end loop;
+		bit1_nxt	<= temp;
+	end process;
+
+	-----------------------------------------------------------------------------
+	-- Register
+	-----------------------------------------------------------------------------
+	process (clk)
+	begin	-- process
+		if rising_edge(clk) then
+			if rst = '1' then
+				val_r <= resize(SEED, BITS);
+			elsif got = '1' then
+				val_r <= val_r(val_r'left - 1 downto 1) & bit1_nxt;
+			end if;
+		end if;
+	end process;
+
+	-----------------------------------------------------------------------------
+	-- Outputs
+	-----------------------------------------------------------------------------
+	val	 <= val_r;
+
+end rtl;
diff --git a/testsuite/gna/bug035/arith_prng_tb.vhdl b/testsuite/gna/bug035/arith_prng_tb.vhdl
@@ -0,0 +1,117 @@
+-- EMACS settings: -*-  tab-width: 2; indent-tabs-mode: t -*-
+-- vim: tabstop=2:shiftwidth=2:noexpandtab
+-- kate: tab-width 2; replace-tabs off; indent-width 2;
+-- 
+-- =============================================================================
+-- Testbench:				Pseudo-Random Number Generator (PRNG).
+-- 
+-- Authors:					Patrick Lehmann
+-- 
+-- Description:
+-- ------------------------------------
+--		Automated testbench for PoC.arith_prng
+--		The Pseudo-Random Number Generator is instantiated for 8 bits. The
+--		output sequence is compared to 256 pre calculated values.
+--
+-- License:
+-- =============================================================================
+-- Copyright 2007-2015 Technische Universitaet Dresden - Germany
+--										 Chair for VLSI-Design, Diagnostics and Architecture
+-- 
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+-- 
+--		http://www.apache.org/licenses/LICENSE-2.0
+-- 
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+-- =============================================================================
+
+LIBRARY IEEE;
+USE			IEEE.STD_LOGIC_1164.ALL;
+USE			IEEE.NUMERIC_STD.ALL;
+
+LIBRARY PoC;
+USE			PoC.utils.ALL;
+USE			PoC.vectors.ALL;
+USE			PoC.strings.ALL;
+USE			PoC.simulation.ALL;
+
+
+ENTITY arith_prng_tb IS
+END;
+
+
+ARCHITECTURE test OF arith_prng_tb IS
+	CONSTANT CLOCK_PERIOD_100MHZ			: TIME															:= 10 ns;
+
+	CONSTANT COMPARE_LIST_8_BITS			: T_SLVV_8(0 TO 255)								:= (
+		x"12", x"24", x"48", x"90", x"21", x"42", x"85", x"0A", x"14", x"28", x"51", x"A2", x"45", x"8B", x"17", x"2E",
+		x"5D", x"BB", x"77", x"EF", x"DE", x"BC", x"79", x"F2", x"E4", x"C9", x"93", x"27", x"4E", x"9C", x"38", x"70",
+		x"E1", x"C3", x"86", x"0C", x"18", x"31", x"63", x"C6", x"8C", x"19", x"33", x"67", x"CE", x"9D", x"3A", x"74",
+		x"E9", x"D2", x"A5", x"4B", x"96", x"2D", x"5B", x"B7", x"6E", x"DD", x"BA", x"75", x"EB", x"D6", x"AD", x"5A",
+		x"B5", x"6A", x"D5", x"AB", x"56", x"AC", x"58", x"B1", x"62", x"C4", x"88", x"11", x"22", x"44", x"89", x"13",
+		x"26", x"4C", x"98", x"30", x"61", x"C2", x"84", x"08", x"10", x"20", x"40", x"81", x"02", x"05", x"0B", x"16",
+		x"2C", x"59", x"B3", x"66", x"CC", x"99", x"32", x"65", x"CA", x"95", x"2B", x"57", x"AE", x"5C", x"B9", x"73",
+		x"E7", x"CF", x"9F", x"3E", x"7C", x"F8", x"F1", x"E2", x"C5", x"8A", x"15", x"2A", x"55", x"AA", x"54", x"A8",
+		x"50", x"A0", x"41", x"83", x"06", x"0D", x"1A", x"35", x"6B", x"D7", x"AF", x"5E", x"BD", x"7B", x"F6", x"EC",
+		x"D8", x"B0", x"60", x"C0", x"80", x"00", x"01", x"03", x"07", x"0F", x"1E", x"3D", x"7A", x"F4", x"E8", x"D0",
+		x"A1", x"43", x"87", x"0E", x"1C", x"39", x"72", x"E5", x"CB", x"97", x"2F", x"5F", x"BF", x"7F", x"FE", x"FD",
+		x"FB", x"F7", x"EE", x"DC", x"B8", x"71", x"E3", x"C7", x"8E", x"1D", x"3B", x"76", x"ED", x"DA", x"B4", x"68",
+		x"D1", x"A3", x"47", x"8F", x"1F", x"3F", x"7E", x"FC", x"F9", x"F3", x"E6", x"CD", x"9B", x"36", x"6D", x"DB",
+		x"B6", x"6C", x"D9", x"B2", x"64", x"C8", x"91", x"23", x"46", x"8D", x"1B", x"37", x"6F", x"DF", x"BE", x"7D",
+		x"FA", x"F5", x"EA", x"D4", x"A9", x"52", x"A4", x"49", x"92", x"25", x"4A", x"94", x"29", x"53", x"A6", x"4D",
+		x"9A", x"34", x"69", x"D3", x"A7", x"4F", x"9E", x"3C", x"78", x"F0", x"E0", x"C1", x"82", x"04", x"09", x"12"
+	);
+
+	SIGNAL SimStop			: std_logic := '0';
+
+	SIGNAL Clock				: STD_LOGIC			:= '1';
+	SIGNAL Reset				: STD_LOGIC			:= '0';
+	SIGNAL Test_got			: STD_LOGIC			:= '0';
+	SIGNAL PRNG_Value		: T_SLV_8;
+
+BEGIN
+
+	Clock <= Clock xnor SimStop after CLOCK_PERIOD_100MHZ / 2.0;
+
+	PROCESS
+	BEGIN
+		WAIT UNTIL rising_edge(Clock);
+
+		Reset						<= '1';
+		WAIT UNTIL rising_edge(Clock);
+
+		Reset						<= '0';
+		WAIT UNTIL rising_edge(Clock);
+
+		FOR I IN 0 TO 255 LOOP
+			Test_got				<= '1';
+			WAIT UNTIL rising_edge(Clock);
+			tbAssert((PRNG_Value = COMPARE_LIST_8_BITS(I)), "I=" & integer'image(I) &	" Value=" & raw_format_slv_hex(PRNG_Value) & " Expected=" & raw_format_slv_hex(COMPARE_LIST_8_BITS(I)));
+		END LOOP;
+
+		-- Report overall simulation result
+		tbPrintResult;
+		SimStop	<= '1';
+                assert now < 3000 ns severity failure;
+		WAIT;
+	END PROCESS;
+
+	prng : entity PoC.arith_prng
+		generic map (
+			BITS		=> 8,
+			SEED		=> x"12"
+		)
+		port map (
+			clk			=> Clock,						
+			rst			=> Reset,						-- reset value to initial seed
+			got			=> Test_got,				-- the current value has been got, and a new value should be calculated
+			val			=> PRNG_Value				-- the pseudo-random number
+		);
+
+END;