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library ieee ; | ||
use ieee.std_logic_1164.all ; | ||
use std.textio.all ; | ||
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entity cond_assign_proc is | ||
end entity cond_assign_proc ; | ||
architecture doit of cond_assign_proc is | ||
signal Clk : std_logic := '0' ; | ||
signal Y : std_logic ; | ||
begin | ||
Clk <= not Clk after 10 ns ; | ||
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process (Clk) | ||
variable A : std_logic ; | ||
begin | ||
A := 'H' when Clk = '1' else 'L' ; | ||
Y <= A ; | ||
-- Y <= 'H' when Clk = '1' else 'L' ; | ||
end process ; | ||
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-- Y <= 'H' when Clk = '1' else 'L' ; | ||
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process | ||
begin | ||
wait for 500 ns ; | ||
std.env.stop ; | ||
end process ; | ||
end architecture doit ; | ||
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library ieee ; | ||
use ieee.std_logic_1164.all ; | ||
use std.textio.all ; | ||
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entity cond_assign_sig is | ||
end entity cond_assign_sig ; | ||
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architecture doit of cond_assign_sig is | ||
signal Clk : std_logic := '0' ; | ||
signal Y : std_logic ; | ||
begin | ||
Clk <= not Clk after 10 ns ; | ||
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process (Clk) | ||
begin | ||
Y <= 'H' when Clk = '1' else 'L' ; | ||
end process ; | ||
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-- Y <= 'H' when Clk = '1' else 'L' ; | ||
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process | ||
begin | ||
wait for 500 ns ; | ||
std.env.stop ; | ||
end process ; | ||
end architecture doit ; | ||
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library ieee ; | ||
use ieee.std_logic_1164.all ; | ||
use std.textio.all ; | ||
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entity cond_assign_var is | ||
end entity cond_assign_var ; | ||
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architecture doit of cond_assign_var is | ||
signal Clk : std_logic := '0' ; | ||
signal Y : std_logic ; | ||
begin | ||
Clk <= not Clk after 10 ns ; | ||
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process (Clk) | ||
variable A : std_logic ; | ||
begin | ||
A := 'H' when Clk = '1' else 'L' ; | ||
Y <= A ; | ||
-- Y <= 'H' when Clk = '1' else 'L' ; | ||
end process ; | ||
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-- Y <= 'H' when Clk = '1' else 'L' ; | ||
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process | ||
begin | ||
wait for 500 ns ; | ||
std.env.stop ; | ||
end process ; | ||
end architecture doit ; | ||
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#! /bin/sh | ||
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. ../../testenv.sh | ||
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GHDL_STD_FLAGS=--std=08 | ||
analyze cond_assign_var.vhdl | ||
elab_simulate cond_assign_var | ||
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analyze cond_assign_sig.vhdl | ||
elab_simulate cond_assign_sig | ||
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analyze cond_assign_proc.vhdl | ||
elab_simulate cond_assign_proc | ||
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clean | ||
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echo "Test successful" |