TYPES.INTERNAL_ERROR : synth-vhdl_oper.adb:57

[Bynaryman]

Description

Easy to reproduce error yield by file src/synth/synth-vhdl_oper line 57.
It happens when the vhdl performs an operation (substraction) with a signal a negative number.

Expected behaviour
I expect to perform an addition.

How to reproduce?

entity ent is
end entity;

architecture a of ent is

signal scale_product_twice_biased :  std_logic_vector(3 downto 0);
signal shift_value :  std_logic_vector(3 downto 0);

begin

   shift_value <= (scale_product_twice_biased) - (-1);

  process begin
    report "Hello world" severity note;
    wait;
  end process;
end;

ghdl -a ent.vhd
ghdl --elab-run ent

NOTE: :file: and :image: identifiers are specific to issue-runner. We suggest to use these, since it allows continuous integration workflows to automatically test the MWE. Using ghdl/ghdl:* docker images to run the MWEs ensures that the latest available GHDL is used.

NOTE: Large files can be uploaded one-by-one or in a tarball/zipfile.

Context
Please, provide the following information:

• OS: Arch linux 5.15.10
• Origin:
  • Package manager: version
  • Released binaries: tarball_url
  • [ x] Built from sources: 25ccaf3

If a GHDL Bug occurred block is shown in the log, please paste it here:

******************** GHDL Bug occurred ***************************
Please report this bug on https://github.com/ghdl/ghdl/issues
GHDL release: 2.0.0-dev (1.0.0.r972.g25ccaf3d) [Dunoon edition]
Compiled with unknown compiler version
Target: x86_64-pc-linux-gnu
/home/binaryman/Documents/perso/vhdl2verilog/
Command line:

Exception TYPES.INTERNAL_ERROR raised
Exception information:
raised TYPES.INTERNAL_ERROR : synth-vhdl_oper.adb:57
******************************************************************
ERROR: vhdl import failed.

Additional context
Hopefully there is enough content to understand. I will be around to provide details if needed. A simple double minus sign makes it fail at line 57 of file synth-vhdl_oper.adb. This line throws an exception. Unfortunately i have no knowledge in this language to propose a pull request. For the moment I fix the vhdl by replace "signal - (-8)" by "signal +8" (for example). The problem is that my vhdl is automatically generated, that is why there is sort of nonsense double "-". Cheers.