Error when entity name is the same as port name #542
Comments
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It would be nice to have a reproducer, as it isn't easy to guess the details. |
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Here it is. I commented the source code in wrapper.vhd to make it a little more clear what are the hacks to do depending on the std. wrapper.vhd: library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity wrapper is
port(
clk : in std_logic;
reset : in std_logic;
write : in std_logic;
ack : out std_logic
);
end wrapper;
architecture a of wrapper is
-- compiling with std=93 produces an error here
component write is
port(
clk : in std_logic;
reset : in std_logic;
write : in std_logic;
ack : out std_logic
);
end component;
begin
--dut : entity work.write(a) -- compilation works with this type of instanciation/declaration, std=08 and component declaration on line 17 commented
dut: component write
port map(
clk => clk,
reset => reset,
write => write, --compiling with std=08 produces a error here
ack => ack
);
end architecture;write.vhd: library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity write is
port(
clk : in std_logic;
reset : in std_logic;
write : in std_logic;
ack : out std_logic
);
end write;
architecture a of write is
begin
process (clk, reset) is
begin
if reset = '1' then
ack <= '0';
elsif rising_edge(clk) then
if write = '1' then
ack <= '1';
else
ack <= '0';
end if;
end if;
end process;
end architecture;First try, std=93Source code as it is $ ghdl -a -g write.vhd wrapper.vhd
wrapper.vhd:16:18:error: identifier "write" already used for a declaration
wrapper.vhd:9:8:error: previous declaration: port "write"
wrapper.vhd:27:23:error: component name expected, found port "write"
ghdl:error: compilation errorSecond try, std=08Source code as it is. Thrid try and successStill std=08, remove component declaration (lines 17 to 24 in wrapper.vhd) and use component "direct" instantiation on line 28, remove line 29. No errors! Some detail |
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This is a little bit subtile as the rules have changed with vhdl 2002. After vhdl 2002, the architecture is a nested declarative region. So the component 'write' overrides the port 'write'. But then in the component instantiation you use 'write' which refers to the component. I will try to make the error message more readable. |
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Thanks for taking this into account. So you're saying that m***lsim does not respect the VHDL standard because it does not issue any warning or errors for any of the 3 precedent cases? |
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@Bamban
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Yes, I don't see how this could be valid. Have you tried with another simulator ? |
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Aldec Riviera-PRO 2017.10 reports the following messages: vcom -93 ... vcom ... (default = 2002) vcom -2008 ... |
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Here is the result for Modelsim Intel FPGA Edition. My first attempt with Modelsim Altera Edition did not raised any errors because ... it is complicated. I use Platform Designer (ex-Qsys) to create a subsystem. I then use the simulation scripts generated by Quartus for this system to analyze and elaborate my subsystem. In this case, the vcom command that concerns my faulty component (nested far away from my own simulation script) does not raise any errors, even in pedantic mode. I don't know why yet. |
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Hi Tristan, but in the VHDL-08 LRM it says: Aren't "nested" and "single" in contradiction? Regards, |
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You're right. I haven't remarked that this has changed again in vhdl 2008.
So they are nested only in vhdl 2002...
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This is even more fun: there is no bar change in the vhdl LRM 2008, so it looks it was not intentional... |
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A last question: |
Hi,
I have a problem with entity name clashing with port name. My code is compiling with Modelsim but not GHDL. Here is the component interface:
The compilation fails when declaring component then instantiating. In vhdl93, it fails at the declaration with:
In vhdl08, it fails at the instantiation with:
The compilation works when using direct instantiation via "dut : entity work.ami_write(behavior)". I'm using this for the moment.
Is there something wrong I'm doing?
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