Coq / Verilog misdetection

[yumaueda]

Coq / Verilog misdetection

Problem Description

Some Verilog files are misclassified as Coq files in my repository. I'm suspicious that Verilog synthesis attribute can cause this. These should be classified as Verilog, I think.

URL of the affected repository:

https://github.com/0x00a1e9/selevy

Last modified on:

2019-12-15

Expected language:

Verilog

Detected language:

Coq

[pchaigno]

Any reason you removed the checkboxes from the templates? Looks like the second and third would have been useful to you...

[lildude]

I opened this just because I thought it's good if the problem I mentioned is kind of one can be fixed.

It certainly can, but it's going to need a PR from someone that understands Coq and Verilog as they both share the same extension and thus the heuristic at https://github.com/github/linguist/blob/643c091e8d1e8c20401d1267ca558d304ebae8ca/lib/linguist/heuristics.yml#L460-L467 ... needs to be enhanced.

If you know of a good regex that can improve the detection rate, please feel free to submit a pull request. If no one submits a PR, this issue is likely to go stale and be automatically closed.

[pchaigno]

I just thought people didn't check items in the template wouldn't open an issue here

Unfortunately, people who don't read that information open issues here all the time.

To complete @lildude's answer, you can also try to add new sample files, if you see that the current ones are not representative enough.

[stale]

This issue has been automatically marked as stale because it has not had activity in a long time. If this issue is still relevant and should remain open, please reply with a short explanation (e.g. "I have checked the code and this issue is still relevant because ___."). Thank you for your contributions.

[stale]

This issue has been automatically closed because it has not had activity in a long time. Please feel free to reopen it or create a new issue.