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Refine definition of KiCad #3743

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merged 5 commits into from Aug 8, 2017
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33 changes: 28 additions & 5 deletions lib/linguist/languages.yml
Expand Up @@ -2137,15 +2137,37 @@ KRL:
tm_scope: none
ace_mode: text
language_id: 186
KiCad:
type: programming
KiCad Board:
type: data
extensions:
- ".sch"
- ".brd"
- ".kicad_pcb"
tm_scope: none
tm_scope: source.pcb.board
ace_mode: text
language_id: 140848857
KiCad Layout:
type: data
aliases:
- pcbnew
extensions:
- ".kicad_pcb"
- ".kicad_mod"
- ".kicad_wks"
filenames:
- fp-lib-table
tm_scope: source.pcb.sexp
ace_mode: lisp
codemirror_mode: commonlisp
codemirror_mime_type: text/x-common-lisp
language_id: 187
KiCad Schematic:
type: data
aliases:
- eeschema schematic
extensions:
- ".sch"
tm_scope: source.pcb.schematic
ace_mode: text
language_id: 622447435
Kit:
type: markup
ace_mode: html
Expand Down Expand Up @@ -4082,6 +4104,7 @@ Scheme:
color: "#1e4aec"
extensions:
- ".scm"
- ".sch"
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No need for a heuristic rule between KiCad Schematic and Scheme?

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Hrm, do you think it warrants one? These were the only non-KiCad files marked as KiCad Schematics, and this was the only KiCad file identified as Scheme. All-in-all, I think the classifier's doing a good enough job. =)

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Ok 👍

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@Alhadis Alhadis Jul 28, 2017

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Travis shat bricks the moment I submitted this PR... any idea what's up with that? 😕

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I think it's due to a recent update of Travis CI's default images. @kivikakk fixed it in her pull request.

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@Alhadis Alhadis Jul 28, 2017

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I trust she knows what she's doing. 👍 'Cause I don't, haha. Thanks!

(I named one of the samples after her, BTW... or rather, I made a typo and decided to keep it because it was so lulzy)

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(I named one of the samples after her, BTW... or rather, I made a typo and decided to keep it because it was so lulzy)

Awwww, this is as nice as the time I got called "Purveyor of the finest kivikode" by a coworker!

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@Alhadis Alhadis Jul 28, 2017

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The extent of my Estonian knowledge in one picture, screen-capped from Notes.app:

screen shot 2017-07-28 at 6 01 06 pm

Also, this.

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I've spent the entire day sorting files into folders, I'm getting jittery and restless. 😆

- ".sld"
- ".sls"
- ".sps"
Expand Down
62 changes: 62 additions & 0 deletions samples/INI/ultimate-temp-controller.pro
@@ -0,0 +1,62 @@
update=22/05/2015 07:44:53
version=1
last_client=kicad
[general]
version=1
RootSch=
BoardNm=
[pcbnew]
version=1
LastNetListRead=
UseCmpFile=1
PadDrill=0.600000000000
PadDrillOvalY=0.600000000000
PadSizeH=1.500000000000
PadSizeV=1.500000000000
PcbTextSizeV=1.500000000000
PcbTextSizeH=1.500000000000
PcbTextThickness=0.300000000000
ModuleTextSizeV=1.000000000000
ModuleTextSizeH=1.000000000000
ModuleTextSizeThickness=0.150000000000
SolderMaskClearance=0.000000000000
SolderMaskMinWidth=0.000000000000
DrawSegmentWidth=0.200000000000
BoardOutlineThickness=0.100000000000
ModuleOutlineThickness=0.150000000000
[cvpcb]
version=1
NetIExt=net
[eeschema]
version=1
LibDir=
[eeschema/libraries]
LibName1=power
LibName2=device
LibName3=transistors
LibName4=conn
LibName5=linear
LibName6=regul
LibName7=74xx
LibName8=cmos4000
LibName9=adc-dac
LibName10=memory
LibName11=xilinx
LibName12=microcontrollers
LibName13=dsp
LibName14=microchip
LibName15=analog_switches
LibName16=motorola
LibName17=texas
LibName18=intel
LibName19=audio
LibName20=interface
LibName21=digital-audio
LibName22=philips
LibName23=display
LibName24=cypress
LibName25=siliconi
LibName26=opto
LibName27=atmel
LibName28=contrib
LibName29=valves
File renamed without changes.
23 changes: 23 additions & 0 deletions samples/KiCad Layout/C_Disc_D3_P2.5.kicad_mod
@@ -0,0 +1,23 @@
(module footprints:C_Disc_D3_P2.5 (layer F.Cu) (tedit 0)
(descr "Capacitor 3mm Disc, Pitch 2.5mm")
(tags Capacitor)
(fp_text reference C1 (at 1.25 -2.5) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value C_100nF (at 1.25 2.5) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -0.9 -1.5) (end 3.4 -1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start 3.4 -1.5) (end 3.4 1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start 3.4 1.5) (end -0.9 1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start -0.9 1.5) (end -0.9 -1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start -0.25 -1.25) (end 2.75 -1.25) (layer F.SilkS) (width 0.15))
(fp_line (start 2.75 1.25) (end -0.25 1.25) (layer F.SilkS) (width 0.15))
(pad 1 thru_hole rect (at 0 0) (size 1.3 1.3) (drill 0.8) (layers *.Cu *.Mask F.SilkS))
(pad 2 thru_hole circle (at 2.5 0) (size 1.3 1.3) (drill 0.8001) (layers *.Cu *.Mask F.SilkS))
(model Capacitors_ThroughHole.3dshapes/C_Disc_D3_P2.5.wrl
(at (xyz 0.0492126 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)