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It looks like resetting the FPGA intrinsically tristates all pins (verify!), and it's not clear that tristating every port (~OEQ is routed to all buffers) on alert in any port is the right thing to do.
The text was updated successfully, but these errors were encountered:
It looks like resetting the FPGA intrinsically tristates all pins (verify!), and it's not clear that tristating every port (~OEQ is routed to all buffers) on alert in any port is the right thing to do.
The text was updated successfully, but these errors were encountered: