Indentation changes, more similar to vhdl-mode, bugfixes

[Rutherther]

Hello,

when using vhdl-ts-mode I noticed some problems with indentation. This PR addresses them. I am not really sure what the intention of this mode is, and whether it should be more similar to vhdl-mode or not. There are two parts to this PR. I think one part should be merged, and the other one is probably more opinionated, and I am not sure you will want to merge it.

First part (bugs)

1. variable_interface_declaration is missing, leading to variable being indented improperly in procedure declaration, see

  procedure trigger_scl_pulse(
                             variable asdf      : in    test;
    signal scl_rising  : inout std_logic;
    signal scl_falling : inout std_logic
  ) is

2. when else with else being on one line, and alternative assignment being on the next line, is aligned to start of else, instead of start of <=. This was reported in vhdl-ts-mode breaks indentation of conditional signal assignment and selected signal assignment statements #6.
3. Empty lines are indented by vhdl-ts-indent-offset, sometimes leading to situations where empty line has different indent then when something ends up being on the line.

Second part (opinionated changes for more similarity to vhdl-mode)

1. port map and generic map are on the same level as first label: entity line, instead of indented more deeply, to indicate they are structurally under that entity.
2. else with when block is aligned one level from assignment <= instead of after <=, like vhdl mode has it

Demonstration

Before

library ieee;
use ieee.std_logic_1164.all;

entity indent_test is

end entity indent_test;

architecture testarchitect of indent_test is
  function asdf (
    constant test : test)
    return trest is
  begin  -- function asdf
    -- empty line alignment
  end function asdf;

    -- empty line alignment

  procedure my_procedure (
    constant const : in std_logic;
                         variable var : in std_logic);
  -- empty line alignment
begin  -- architecture testarchitect

  -- empty line alignment

  label: entity work.my_entity
  port map (
    test => test);

  NSL : state_next <= RED_YELLOW when state_reg = RED and button = '1' else
                                                                       GREEN  when state_reg = RED_YELLOW
    else YELLOW when state_reg = GREEN and button = '1' else
                                                        RED when state_reg = YELLOW else
                                                                                    state_reg;
    -- this line has been typed without aligning it afterwards, only aligning
    -- it prior to typing when it was emtpy

  -- this is after beautify

  OL : with state_reg select
  leds <=
  "100" when RED,
                "110" when RED_YELLOW,
                                     "001" when GREEN,
                                                     "010" when YELLOW,
                                                                      "---" when others;
  -- empty line alignment

end architecture testarchitect;

After

library ieee;
use ieee.std_logic_1164.all;

entity indent_test is

end entity indent_test;

architecture testarchitect of indent_test is
  -- empty line alignment

  function asdf (
    constant test : test)
    return trest is
  begin  -- function asdf
    -- empty line alignment
  end function asdf;

  -- empty line alignment

  procedure my_procedure (
    constant const : in std_logic;
    variable var : in std_logic);

  -- empty line alignment
begin  -- architecture testarchitec

  -- empty line alignment

  label: entity work.my_entity
    port map (
      test => test);

  NSL : state_next <= RED_YELLOW when state_reg = RED and button = '1' else
                      GREEN  when state_reg = RED_YELLOW else
                      YELLOW when state_reg = GREEN and button = '1'
                      else RED when state_reg = YELLOW else
                      state_reg;

  -- this line has been typed without aligning it afterwards, only aligning
  -- it prior to typing when it was emtpy

  OL : with state_reg select
  leds <=
    "100" when RED,
    "110" when RED_YELLOW,
    "001" when GREEN,
    "010" when YELLOW,
    "---" when others;


  -- empty line alignment


end architecture testarchitect;

[Rutherther]

Added fix to indent leds here:

  OL : with state_reg select
    leds <=
    "100" when RED,
    "110" when RED_YELLOW,
    "001" when GREEN,
    "010" when YELLOW,
    "---" when others;

[maehne]

Looks good to me.