AMD: I think that's Navi.

.gitignore

@@ -5,3 +5,4 @@
 *.o
 *.symvers
 *.order
+*.d

src/amd/Makefile

@@ -9,6 +9,8 @@ vendor-reset-y += \
 	src/amd/amdgpu/common_baco.o \
 	src/amd/amdgpu/vega10_reg_init.o \
 	src/amd/amdgpu/navi10_reg_init.o \
+	src/amd/amdgpu/navi12_reg_init.o \
+	src/amd/amdgpu/navi14_reg_init.o \
 	src/amd/amdgpu/amdgpu_device.o \
 	src/amd/amdgpu/amdgpu_discovery.o \
 	src/amd/amdgpu/atom.o \

src/amd/amd.h

@@ -16,7 +16,20 @@ this program; if not, write to the Free Software Foundation, Inc., 59 Temple
 Place, Suite 330, Boston, MA 02111-1307 USA
 */
 
-extern struct vendor_reset_ops amd_polaris10_ops;
-extern struct vendor_reset_ops amd_vega10_ops;
-extern struct vendor_reset_ops amd_vega20_ops;
-extern struct vendor_reset_ops amd_navi10_ops;
+enum amd_device_type
+{
+  AMD_POLARIS10,
+  AMD_POLARIS11,
+  AMD_POLARIS12,
+  AMD_VEGA10,
+  AMD_VEGA12,
+  AMD_VEGA20,
+  AMD_NAVI10,
+  AMD_NAVI12,
+  AMD_NAVI14,
+};
+
+extern const struct vendor_reset_ops amd_polaris10_ops;
+extern const struct vendor_reset_ops amd_vega10_ops;
+extern const struct vendor_reset_ops amd_vega20_ops;
+extern const struct vendor_reset_ops amd_navi10_ops;

src/amd/amdgpu/include/smu_v11_0.h

@@ -0,0 +1,57 @@
+/*
+ * Copyright 2019 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+#ifndef __SMU_V11_0_H__
+#define __SMU_V11_0_H__
+
+#define SMU11_DRIVER_IF_VERSION_INV 0xFFFFFFFF
+#define SMU11_DRIVER_IF_VERSION_ARCT 0x17
+#define SMU11_DRIVER_IF_VERSION_NV10 0x36
+#define SMU11_DRIVER_IF_VERSION_NV12 0x33
+#define SMU11_DRIVER_IF_VERSION_NV14 0x36
+#define SMU11_DRIVER_IF_VERSION_Sienna_Cichlid 0x34
+#define SMU11_DRIVER_IF_VERSION_Navy_Flounder 0x3
+
+/* MP Apertures */
+#define MP0_Public 0x03800000
+#define MP0_SRAM 0x03900000
+#define MP1_Public 0x03b00000
+#define MP1_SRAM 0x03c00004
+
+/* address block */
+#define smnMP1_FIRMWARE_FLAGS 0x3010024
+#define smnMP0_FW_INTF 0x30101c0
+#define smnMP1_PUB_CTRL 0x3010b14
+
+#define TEMP_RANGE_MIN (0)
+#define TEMP_RANGE_MAX (80 * 1000)
+
+#define SMU11_TOOL_SIZE 0x19000
+
+#define MAX_DPM_LEVELS 16
+#define MAX_PCIE_CONF 2
+
+#define CTF_OFFSET_EDGE 5
+#define CTF_OFFSET_HOTSPOT 5
+#define CTF_OFFSET_MEM 5
+
+#endif