Here we provide resources for the workshop itself, as well as additional resources related to the "Design a Chip in a Day" competition.
For RTL-based design, go to the RTL_based_design folder.
For HLS-based design, go to the HLS folder.
- You need to register for DAC (i.e., full conference registration) in order to attend the GREAT workshop and participate in the competition.
- Only use an LLM to generate the RTL/C/C++.
- Minor manual fixes to LLM-generated codes are allowed, e.g., fixing minor syntax issues such as missing keywords or ";".
- Major manual corrections/coding will incur a penalty.
- Participants will be required to submit the LLM conversation links for all submitted codes in order to be eligible for evaluation.
- Participants will be provided with the top module declaration (containing primary input and output signal names) and a testbench for the top module to verify their final design.
- Participants are free to have a hierarchical design and to write custom testbenches for submodules, as long as the top module is according to the provided declaration and is compatible with the provided testbench.
- The submissions will be evaluated by a panel of judges. Overall, the evaluations shall be performed based on functional correctness (using the provided testbench) and PPA metrics.
- The organizers reserve the right to disqualify any entry that does not comply with the competition rules.
- The organizers reserve the right to make the final judgment in any dispute or situation not covered by these rules.
- The organizers' decisions regarding the interpretation of the rules are at their sole discretion and are not subject to appeal.
- The organizers reserve the right to amend these rules at any time. Any changes will be reflected here and/or communicated to participants promptly.
Once you have successfully generated the code using the LLM and are ready to submit, you can do so using this Google Form: link