Added 1500Mhz + voltage.

gained 10~15% more in benchmarks, and stable.
gokhanmoral · Apr 17, 2012 · cf1cc8b · cf1cc8b
1 parent ce5d578
commit cf1cc8b
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Showing 3 changed files with 55 additions and 42 deletions.
diff --git a/arch/arm/configs/dorimanx_defconfig b/arch/arm/configs/dorimanx_defconfig
@@ -80,13 +80,12 @@ CONFIG_RCU_FANOUT=32
 # CONFIG_IKCONFIG is not set
 CONFIG_LOG_BUF_SHIFT=18
 CONFIG_CGROUPS=y
-CONFIG_CGROUP_DEBUG=y
-CONFIG_CGROUP_FREEZER=y
+# CONFIG_CGROUP_DEBUG is not set
+# CONFIG_CGROUP_FREEZER is not set
 # CONFIG_CGROUP_DEVICE is not set
 # CONFIG_CPUSETS is not set
 CONFIG_CGROUP_CPUACCT=y
-CONFIG_RESOURCE_COUNTERS=y
-# CONFIG_CGROUP_MEM_RES_CTLR is not set
+# CONFIG_RESOURCE_COUNTERS is not set
 # CONFIG_CGROUP_PERF is not set
 CONFIG_CGROUP_SCHED=y
 CONFIG_FAIR_GROUP_SCHED=y

diff --git a/arch/arm/mach-exynos/cpufreq-4210.c b/arch/arm/mach-exynos/cpufreq-4210.c
@@ -23,7 +23,7 @@
 
 #include <plat/clock.h>
 
-#define CPUFREQ_LEVEL_END	L6
+#define CPUFREQ_LEVEL_END	L7
 
 static int max_support_idx;
 static int min_support_idx = (CPUFREQ_LEVEL_END - 1);
@@ -40,12 +40,13 @@ struct cpufreq_clkdiv {
 static unsigned int exynos4210_volt_table[CPUFREQ_LEVEL_END];
 
 static struct cpufreq_frequency_table exynos4210_freq_table[] = {
-	{L0, 1400*1000},
-	{L1, 1200*1000},
-	{L2, 1000*1000},
-	{L3, 800*1000},
-	{L4, 500*1000},
-	{L5, 200*1000},
+	{L0, 1500*1000},
+        {L1, 1400*1000},
+	{L2, 1200*1000},
+	{L3, 1000*1000},
+	{L4, 800*1000},
+	{L5, 500*1000},
+	{L6, 200*1000},
 	{0, CPUFREQ_TABLE_END},
 };
 
@@ -56,6 +57,7 @@ static struct cpufreq_clkdiv exynos4210_clkdiv_table[] = {
 	{L3, 0},
 	{L4, 0},
 	{L5, 0},
+        {L6, 0},
 };
 
 static unsigned int clkdiv_cpu0[CPUFREQ_LEVEL_END][7] = {
@@ -64,6 +66,8 @@ static unsigned int clkdiv_cpu0[CPUFREQ_LEVEL_END][7] = {
 	 * { DIVCORE, DIVCOREM0, DIVCOREM1, DIVPERIPH,
 	 *		DIVATB, DIVPCLK_DBG, DIVAPLL }
 	 */
+        /* ARM L0: 1500MHz */
+        { 0, 3, 7, 3, 4, 1, 7 },
 	/* ARM L0: 1400MHz */
 	{ 0, 3, 7, 3, 4, 1, 7 },
 
@@ -87,42 +91,47 @@ static unsigned int clkdiv_cpu1[CPUFREQ_LEVEL_END][2] = {
 	/* Clock divider value for following
 	 * { DIVCOPY, DIVHPM }
 	 */
-	/* ARM L0: 1400MHz */
+        /* ARM L0: 1400MHz */
+        { 5, 0 },
+	/* ARM L1: 1400MHz */
 	{ 5, 0 },
 
-	/* ARM L1: 1200MHz */
+	/* ARM L2: 1200MHz */
 	{ 5, 0 },
 
-	/* ARM L2: 1000MHz */
+	/* ARM L3: 1000MHz */
 	{ 4, 0 },
 
-	/* ARM L3: 800MHz */
+	/* ARM L4: 800MHz */
 	{ 3, 0 },
 
-	/* ARM L4: 500MHz */
+	/* ARM L5: 500MHz */
 	{ 3, 0 },
 
-	/* ARM L5: 200MHz */
+	/* ARM L6: 200MHz */
 	{ 3, 0 },
 };
 
 static unsigned int exynos4_apll_pms_table[CPUFREQ_LEVEL_END] = {
-	/* APLL FOUT L0: 1400MHz */
+	/* APLL FOUT L0: 1500MHz */
+	((375<<16)|(6<<8)|(0x1)),
+
+	/* APLL FOUT L1: 1400MHz */
 	((350<<16)|(6<<8)|(0x1)),
 
-	/* APLL FOUT L1: 1200MHz */
+	/* APLL FOUT L2: 1200MHz */
 	((150<<16)|(3<<8)|(0x1)),
 
-	/* APLL FOUT L2: 1000MHz */
+	/* APLL FOUT L3: 1000MHz */
 	((250<<16)|(6<<8)|(0x1)),
 
-	/* APLL FOUT L3: 800MHz */
+	/* APLL FOUT L4: 800MHz */
 	((200<<16)|(6<<8)|(0x1)),
 
-	/* APLL FOUT L4: 500MHz */
+	/* APLL FOUT L5: 500MHz */
 	((250<<16)|(6<<8)|(0x2)),
 
-	/* APLL FOUT L5: 200MHz */
+	/* APLL FOUT L6: 200MHz */
 	((200<<16)|(6<<8)|(0x3)),
 };
 
@@ -134,12 +143,15 @@ static const unsigned int asv_voltage_A[CPUFREQ_LEVEL_END][8] = {
 	/*
 	 *	   SS, A1, A2, B1, B2, C1, C2, D
 	 * @Dummy:
+	 * @1500 :
+	 * @1400 :
 	 * @1200 :
 	 * @1000 :
 	 * @800	 :	ASV_VOLTAGE_TABLE
 	 * @500  :
 	 * @200  :
 	 */
+	{ 1450000, 1425000, 1400000, 1375000, 1350000, 1325000, 1300000, 1275000 },
 	{ 1400000, 1400000, 1375000, 1350000, 1350000, 1300000, 1300000, 1300000 },
 	{ 1350000, 1350000, 1300000, 1275000, 1250000, 1225000, 1200000, 1175000 },
 	{ 1300000, 1250000, 1200000, 1175000, 1150000, 1125000, 1100000, 1075000 },
@@ -152,6 +164,7 @@ static const unsigned int asv_voltage_A[CPUFREQ_LEVEL_END][8] = {
 static const unsigned int asv_voltage_B[CPUFREQ_LEVEL_END][5] = {
 	/*
 	 *	   S, A, B, C, D
+	 * @1500 :
 	 * @1400 :
 	 * @1200 :
 	 * @1000 :
@@ -160,6 +173,7 @@ static const unsigned int asv_voltage_B[CPUFREQ_LEVEL_END][5] = {
 	 * @200	 :
 	 */
 	{ 1350000, 1350000, 1300000, 1250000, 1225000 },
+	{ 1350000, 1350000, 1300000, 1250000, 1225000 },
 	{ 1325000, 1275000, 1225000, 1175000, 1150000 },
 	{ 1225000, 1175000, 1125000, 1075000, 1050000 },
 	{ 1150000, 1100000, 1050000, 1000000,  975000 },
@@ -310,11 +324,11 @@ static void __init set_volt_table(void)
 		break;
 	case SUPPORT_1000MHZ:
 		for_1000 = true;
-		max_support_idx = L2;
+		max_support_idx = L3;
 		break;
 	default:
 		for_1000 = true;
-		max_support_idx = L2;
+		max_support_idx = L3;
 		break;
 	}
 
@@ -326,7 +340,7 @@ static void __init set_volt_table(void)
 //		exynos4210_freq_table[L0].frequency = CPUFREQ_ENTRY_INVALID;
 
 	if (for_1000)
-		exynos4210_freq_table[L1].frequency = CPUFREQ_ENTRY_INVALID;
+		exynos4210_freq_table[L2].frequency = CPUFREQ_ENTRY_INVALID;
 
 	printk(KERN_INFO "DVFS : VDD_ARM Voltage table set with %d Group\n", asv_group);
 
@@ -414,17 +428,17 @@ int exynos4210_cpufreq_init(struct exynos_dvfs_info *info)
 	}
 
 	info->mpll_freq_khz = rate;
-	info->pm_lock_idx = L3;
-	info->pll_safe_idx = L2;
+	info->pm_lock_idx = L4;
+	info->pll_safe_idx = L3;
 	info->max_support_idx = max_support_idx;
 	info->min_support_idx = min_support_idx;
 	info->cpu_clk = cpu_clk;
 	info->volt_table = exynos4210_volt_table;
 	info->freq_table = exynos4210_freq_table;
 	info->set_freq = exynos4210_set_frequency;
 	info->need_apll_change = exynos4210_pms_change;
-	info->max_current_idx = L1;
-	info->min_current_idx = L5;
+	info->max_current_idx = L2;
+	info->min_current_idx = L6;
 
 	return 0;
 

diff --git a/arch/arm/mach-exynos/cpufreq.c b/arch/arm/mach-exynos/cpufreq.c
@@ -494,16 +494,16 @@ static int exynos_cpufreq_notifier_event(struct notifier_block *this,
 			mutex_lock(&set_freq_lock);
 
 			/* get the voltage value */
-			safe_arm_volt = exynos_get_safe_armvolt(exynos_info->pm_lock_idx, min(exynos_info->max_current_idx,L1));
+			safe_arm_volt = exynos_get_safe_armvolt(exynos_info->pm_lock_idx, min(exynos_info->max_current_idx, L1));
 			if (safe_arm_volt)
 				regulator_set_voltage(arm_regulator, safe_arm_volt,
 					safe_arm_volt + 25000);
 
-			arm_volt = volt_table[min(exynos_info->max_current_idx,L1)];
+			arm_volt = volt_table[min(exynos_info->max_current_idx, L1)];
 			regulator_set_voltage(arm_regulator, arm_volt,
 				arm_volt + 25000);
 
-			exynos_info->set_freq(exynos_info->pm_lock_idx, min(exynos_info->max_current_idx,L1));
+			exynos_info->set_freq(exynos_info->pm_lock_idx, min(exynos_info->max_current_idx, L1));
 
 			mutex_unlock(&set_freq_lock);
 		}
@@ -750,17 +750,17 @@ ssize_t store_UV_mV_table(struct cpufreq_policy *policy,
 	unsigned int ret = -EINVAL;
 	int i = 0;
 	int j = 0;
-	int u[6];
-	ret = sscanf(buf, "%d %d %d %d %d %d", &u[0], &u[1], &u[2], &u[3], &u[4], &u[5]);
-	if(ret != 6) {
-		ret = sscanf(buf, "%d %d %d %d %d", &u[0], &u[1], &u[2], &u[3], &u[4]);
-		if(ret != 5) {
-			ret = sscanf(buf, "%d %d %d %d", &u[0], &u[1], &u[2], &u[3]);
-			if( ret != 4) return -EINVAL;
+	int u[7];
+	ret = sscanf(buf, "%d %d %d %d %d %d %d", &u[0], &u[1], &u[2], &u[3], &u[4], &u[5], &u[6]);
+	if(ret != 7) {
+		ret = sscanf(buf, "%d %d %d %d %d %d", &u[0], &u[1], &u[2], &u[3], &u[4], &u[5]);
+		if(ret != 6) {
+			ret = sscanf(buf, "%d %d %d %d %d", &u[0], &u[1], &u[2], &u[3], &u[4]);
+			if( ret != 5) return -EINVAL;
 		}
 	}
 
-	for( i = 0; i < 6; i++ )
+	for( i = 0; i < 7; i++ )
 	{
 		if (u[i] > CPU_UV_MV_MAX / 1000)
 		{
@@ -772,7 +772,7 @@ ssize_t store_UV_mV_table(struct cpufreq_policy *policy,
 		}
 	}
 
-	for( i = 6 - ret; i < 6; i++)
+	for( i = 7 - ret; i < 7; i++)
 	{
 		exynos_info->volt_table[i] = u[i]*1000;
 	}