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cpu: add support for sve2 detection
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Fixes golang/go#66952

Change-Id: Idaf2ce3b09baf33cf29079677a83a51ea9c4b255
GitHub-Last-Rev: eac0088
GitHub-Pull-Request: #193
Reviewed-on: https://go-review.googlesource.com/c/sys/+/580655
Reviewed-by: Ian Lance Taylor <iant@google.com>
LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com>
Auto-Submit: Ian Lance Taylor <iant@google.com>
Reviewed-by: David Chase <drchase@google.com>
Reviewed-by: Tobias Klauser <tobias.klauser@gmail.com>
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mhr3 authored and gopherbot committed May 3, 2024
1 parent 9a28524 commit 7758090
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Showing 5 changed files with 25 additions and 0 deletions.
1 change: 1 addition & 0 deletions cpu/cpu.go
Original file line number Diff line number Diff line change
Expand Up @@ -103,6 +103,7 @@ var ARM64 struct {
HasASIMDDP bool // Advanced SIMD double precision instruction set
HasSHA512 bool // SHA512 hardware implementation
HasSVE bool // Scalable Vector Extensions
HasSVE2 bool // Scalable Vector Extensions 2
HasASIMDFHM bool // Advanced SIMD multiplication FP16 to FP32
_ CacheLinePad
}
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10 changes: 10 additions & 0 deletions cpu/cpu_arm64.go
Original file line number Diff line number Diff line change
Expand Up @@ -28,6 +28,7 @@ func initOptions() {
{Name: "sm3", Feature: &ARM64.HasSM3},
{Name: "sm4", Feature: &ARM64.HasSM4},
{Name: "sve", Feature: &ARM64.HasSVE},
{Name: "sve2", Feature: &ARM64.HasSVE2},
{Name: "crc32", Feature: &ARM64.HasCRC32},
{Name: "atomics", Feature: &ARM64.HasATOMICS},
{Name: "asimdhp", Feature: &ARM64.HasASIMDHP},
Expand Down Expand Up @@ -164,6 +165,15 @@ func parseARM64SystemRegisters(isar0, isar1, pfr0 uint64) {
switch extractBits(pfr0, 32, 35) {
case 1:
ARM64.HasSVE = true

parseARM64SVERegister(getzfr0())
}
}

func parseARM64SVERegister(zfr0 uint64) {
switch extractBits(zfr0, 0, 3) {
case 1:
ARM64.HasSVE2 = true
}
}

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8 changes: 8 additions & 0 deletions cpu/cpu_arm64.s
Original file line number Diff line number Diff line change
Expand Up @@ -29,3 +29,11 @@ TEXT ·getpfr0(SB),NOSPLIT,$0-8
WORD $0xd5380400
MOVD R0, ret+0(FP)
RET

// func getzfr0() uint64
TEXT ·getzfr0(SB),NOSPLIT,$0-8
// get SVE Feature Register 0 into x0
// mrs x0, ID_AA64ZFR0_EL1 = d5380480
WORD $0xd5380480
MOVD R0, ret+0(FP)
RET
1 change: 1 addition & 0 deletions cpu/cpu_gc_arm64.go
Original file line number Diff line number Diff line change
Expand Up @@ -9,3 +9,4 @@ package cpu
func getisar0() uint64
func getisar1() uint64
func getpfr0() uint64
func getzfr0() uint64
5 changes: 5 additions & 0 deletions cpu/cpu_linux_arm64.go
Original file line number Diff line number Diff line change
Expand Up @@ -35,6 +35,8 @@ const (
hwcap_SHA512 = 1 << 21
hwcap_SVE = 1 << 22
hwcap_ASIMDFHM = 1 << 23

hwcap2_SVE2 = 1 << 1
)

// linuxKernelCanEmulateCPUID reports whether we're running
Expand Down Expand Up @@ -104,6 +106,9 @@ func doinit() {
ARM64.HasSHA512 = isSet(hwCap, hwcap_SHA512)
ARM64.HasSVE = isSet(hwCap, hwcap_SVE)
ARM64.HasASIMDFHM = isSet(hwCap, hwcap_ASIMDFHM)

// HWCAP2 feature bits
ARM64.HasSVE2 = isSet(hwCap2, hwcap2_SVE2)
}

func isSet(hwc uint, value uint) bool {
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