VHDL description of 6502 processor with FPGA synthesis support.
The design progress is tested using QuestaSim Version 10.0b. In order to simulate it, head to ../sim directory inside Questa and execute "simulate.tcl" with "do" command. Plan Ahead 14.7 is used to synthesise the design, target board is Nexis 3 with Spartan 6 FPGA.
Specific information about the implementation can be found in comments inside source files.