Merge pull request #760 from google/serv_impl_merged

Updates to run Serv in CFU Playground

.gitmodules

@@ -71,3 +71,6 @@
 [submodule "third_party/python/vizier"]
 	path = third_party/python/vizier
 	url = https://github.com/ShvetankPrakash/vizier.git
+[submodule "soc/deps/pythondata_cpu_serv"]
+	path = third_party/python/pythondata_cpu_serv
+	url = https://github.com/litex-hub/pythondata-cpu-serv.git

common/Makefile

@@ -37,6 +37,7 @@ LIBBASE_DIR    := $(SOC_SOFTWARE_DIR)/libbase
 LIBC_DIR       := $(CFU_ROOT)/third_party/python/pythondata-software-picolibc/pythondata_software_picolibc/data/newlib/libc
 LITEX_DIR      := $(CFU_ROOT)/third_party/python/litex/litex
 VEX_SRC_DIR    := $(LITEX_DIR)/soc/cores/cpu/vexriscv
+SERV_SRC_DIR    := $(LITEX_DIR)/soc/cores/cpu/serv
 LITEX_HW_DIR   := $(LITEX_DIR)/soc/software/include
 PYRUN          := $(CFU_ROOT)/scripts/pyrun
 FIX_CFU_DIS    := $(PYRUN) $(CFU_ROOT)/scripts/fix_cfu_dis.py
@@ -66,6 +67,7 @@ SHARED_FLAGS := \
 	-I$(LIBC_DIR)/include \
     -I$(LITEX_HW_DIR) \
     -I$(VEX_SRC_DIR) \
+	-I$(SERV_SRC_DIR) \
 	-ffunction-sections \
 	-fdata-sections \
 	-fno-common \

common/src/base.c

@@ -30,12 +30,15 @@
 
 void isr(void) {
   __attribute__((unused)) unsigned int irqs;
-
+#ifdef UART_INTERRUPT
   irqs = irq_pending() & irq_getmask();
 
   if (irqs & (1 << UART_INTERRUPT)) {
+#endif
     uart_isr();
+#ifdef UART_INTERRUPT
   }
+#endif
 }
 
 void trap_handler(uint32_t* reg_base) {
@@ -47,8 +50,10 @@ void trap_handler(uint32_t* reg_base) {
 }
 
 void init_runtime() {
+#ifdef UART_INTERRUPT
   irq_setmask(0);
   irq_setie(1);
+#endif
   uart_init();
 }
 

common/src/perf.h

@@ -19,6 +19,9 @@
 
 #include "generated/soc.h"
 #include <stdint.h>
+#include <stdio.h>
+#include "generated/csr.h"
+
 
 #ifdef __cplusplus
 extern "C" {
@@ -49,6 +52,8 @@ inline unsigned perf_get_mcycle() {
   return result;
 }
 
+
+
 // Reads both halves of the cycle counter.
 //
 // The value of the counter is stored across two 32-bit registers: `mcycle` and
@@ -220,6 +225,23 @@ inline void perf_disable_counter(int counter_num) {
   perf_set_counter_enable(counter_num, 0);
 }
 
+#ifdef USE_LITEX_TIMER
+static void inline perf_reset_litex_timer(){
+  timer_en_write(0); 
+  timer_reload_write(0); 
+  timer_load_write(0xffffffff); 
+  timer_en_write(1);
+  return;
+} 
+
+static inline uint64_t perf_get_litex_timer() { 
+  uint64_t result; 
+  timer_update_value_write(1); 
+  result = timer_value_read(); 
+  return result; 
+}
+#endif
+
 // Print a human readable number (useful for perf counters)
 void perf_print_human(uint64_t n);
 
@@ -236,6 +258,7 @@ void perf_print_all_counters();
 // Test menu
 void perf_test_menu(void);
 
+
 #ifdef __cplusplus
 }
 #endif

common/src/third_party/embench_iot_v1/src/embench_wrapper.c

@@ -17,6 +17,21 @@
 #include "third_party/embench_iot_v1/support/support.h"
 #include "perf.h"
 #include <stdio.h>
+#include "generated/csr.h"
+
+
+#ifdef USE_LITEX_TIMER
+#define TIMER_TYPE    uint64_t
+#define RESET_TIMER() perf_reset_litex_timer()
+#define GET_TIMER()   perf_get_litex_timer()
+#define PRINT_PERF(a, b)  printf("Spent %llu cycles\n", a - b) 
+#else // default timer to use is mcycle
+#define TIMER_TYPE    unsigned int
+#define RESET_TIMER() /* no reset for mcycle */
+#define GET_TIMER()   perf_get_mcycle() 
+#define PRINT_PERF(a, b)  printf("Spent %u cycles\n", b - a) 
+#endif
+
 
 #define EMBENCH_WRAPPER(benchname) \
 void embench_wrapper_##benchname () \
@@ -25,14 +40,16 @@ void embench_wrapper_##benchname () \
   int correct; \
   initialise_benchmark_##benchname (); \
   warm_caches_##benchname (WARMUP_HEAT); \
-  unsigned int start = perf_get_mcycle(); \
+  RESET_TIMER(); \
+  TIMER_TYPE start = GET_TIMER(); \
   result = benchmark_##benchname (); \
-  unsigned int end = perf_get_mcycle(); \
+  TIMER_TYPE end = GET_TIMER(); \
   correct = verify_benchmark_##benchname (result); \
   printf("%s\n", correct ? "OK  Benchmark result verified" : "FAIL  Benchmark result incorrect"); \
-  printf("Spent %u cycles\n", end - start); \
+  PRINT_PERF(start, end); \
 }
 
+
 #if defined(INCLUDE_EMBENCH_PRIMECOUNT) || defined(INCLUDE_ALL_EMBENCH_EXAMPLES)
     EMBENCH_WRAPPER(primecount)
 #endif

proj/proj.mk

@@ -47,6 +47,11 @@
 # $ make load PLATFORM=sim
 
 export UART_SPEED ?= 1843200
+# Need a slower baudrate when communicating with Serv
+ifdef SERV
+export UART_SPEED = 115200
+endif
+
 export PROJ       := $(lastword $(subst /, ,${CURDIR}))
 export CFU_ROOT   := $(realpath $(CURDIR)/../..)
 export PLATFORM   ?= common_soc

scripts/setup

@@ -12,6 +12,7 @@ git submodule update --init
 # only these submodules need a recursive update
 git submodule update --init --recursive third_party/python/pythondata-software-picolibc
 git submodule update --init --recursive third_party/python/pythondata_cpu_vexriscv
+git submodule update --init --recursive third_party/python/pythondata_cpu_serv
 
 CFU_ROOT="$(dirname $(dirname $(realpath ${BASH_SOURCE[0]})))"
 

soc/patch_cpu_variant.py

@@ -18,15 +18,16 @@
 # pylint:disable=E1101
 
 from litex import get_data_mod
-from litex.soc.cores.cpu.vexriscv import core
+from litex.soc.cores.cpu.vexriscv import core as vexriscv_core
+from litex.soc.cores.cpu.serv     import core as serv_core
 from shutil import copyfile
 
 import os
 
 
 def patch_cpu_variant():
     """Monkey patches custom variants into LiteX."""
-    core.CPU_VARIANTS.update({
+    vexriscv_core.CPU_VARIANTS.update({
         'fomu':                 'VexRiscv_Fomu',
         'fomu+cfu':             'VexRiscv_FomuCfu',
         'custom':               'VexRiscv_Custom',
@@ -45,7 +46,7 @@ def patch_cpu_variant():
         'slimperf+cfu':         'VexRiscv_SlimPerfCfu',
         'slimperf+cfu+debug':   'VexRiscv_SlimPerfCfuDebug',
     })
-    core.GCC_FLAGS.update({
+    vexriscv_core.GCC_FLAGS.update({
         'fomu':                 '-march=rv32im -mabi=ilp32 -mno-div',
         'fomu+cfu':             '-march=rv32im -mabi=ilp32 -mno-div',
         'custom':               '-march=rv32im -mabi=ilp32',
@@ -73,7 +74,7 @@ def patch_cpu_variant():
     })
 
     ########### ADD code to existing add_soc_components() #######
-    old_add_soc_components = core.VexRiscv.add_soc_components
+    old_add_soc_components = vexriscv_core.VexRiscv.add_soc_components
 
     def new_add_soc_components(self, soc, soc_region_cls):
         old_add_soc_components(self, soc, soc_region_cls)
@@ -88,7 +89,7 @@ def new_add_soc_components(self, soc, soc_region_cls):
             # This is here to avoid the dcache flush instruction (system.h).
             soc.constants.pop('CONFIG_CPU_HAS_DCACHE', None)
 
-    core.VexRiscv.add_soc_components = new_add_soc_components
+    vexriscv_core.VexRiscv.add_soc_components = new_add_soc_components
 
 
 
@@ -99,8 +100,8 @@ def new_add_soc_components(self, soc, soc_region_cls):
 #  where the LiteX build expects to find it.
 ################################################################
 def copy_cpu_variant_if_needed(variant):
-    if variant in core.CPU_VARIANTS:
-        cpu_filename = core.CPU_VARIANTS[variant] + ".v"
+    if variant in vexriscv_core.CPU_VARIANTS:
+        cpu_filename = vexriscv_core.CPU_VARIANTS[variant] + ".v"
         vdir = get_data_mod("cpu", "vexriscv").data_location
         fullpath = os.path.join(vdir, cpu_filename)
 
@@ -124,12 +125,12 @@ def copy_cpu_variant_if_needed(variant):
 # This builds a CPU variant on demand 
 ################################################################
 def build_cpu_variant_if_needed(variant):
-    if variant in core.CPU_VARIANTS:
+    if variant in vexriscv_core.CPU_VARIANTS or variant in serv_core.CPU_VARIANTS:
         print(f"Variant \"{variant}\" already known.")
         return
 
     ########### ADD code to existing add_soc_components() #######
-    old_add_soc_components = core.VexRiscv.add_soc_components
+    old_add_soc_components = vexriscv_core.VexRiscv.add_soc_components
 
     def new_add_soc_components(self, soc, soc_region_cls):
         old_add_soc_components(self, soc, soc_region_cls)
@@ -143,7 +144,7 @@ def new_add_soc_components(self, soc, soc_region_cls):
             # This is here to avoid the dcache flush instruction (system.h).
             soc.constants.pop('CONFIG_CPU_HAS_ICACHE', None)
 
-    core.VexRiscv.add_soc_components = new_add_soc_components
+    vexriscv_core.VexRiscv.add_soc_components = new_add_soc_components
 
     cpu_params = {
         "csrPluginConfig":    "mcycle",
@@ -160,7 +161,12 @@ def new_add_soc_components(self, soc, soc_region_cls):
     }
 
     # Parse variant into param list w/o 'generate' keyword
-    params = variant.split("+")[1:]
+    params = variant.split("+")
+    if params[0] != "generate":
+        print("ERROR: Need generate keyword to begin on demand Vexriscv build.")
+        exit()
+
+    params = params[1:]
     for param in params:
         if "cfu" in param:
             cpu_params[param] = "true"
@@ -219,10 +225,10 @@ def new_add_soc_components(self, soc, soc_region_cls):
 
 
 
-    core.CPU_VARIANTS.update({
+    vexriscv_core.CPU_VARIANTS.update({
         variant:             cpu_filename_base,
     })
-    core.GCC_FLAGS.update({
+    vexriscv_core.GCC_FLAGS.update({
         variant:             gcc_flags,
     })